have to remove dcbz from pimem.py entirely

[soc.git] / src / soc / experiment / pimem.py

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 3db68c176cc1fafa2b07dc751ef89219302ceb23..f9aa37df7c981b5a623b6b50b2231731e165ae49 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -258,14 +258,14 @@ class PortInterfaceBase(Elaboratable):
 
         # if now in "DCBZ" mode: wait for addr_ok, then send the address out
         # to memory, acknowledge address, and send out LD data
-        with m.If(dcbz_active.q):
+        #with m.If(dcbz_active.q):
             ##comb += Display("dcbz active")
             # XXX Please don't do it this way, not without discussion
             # the exact same address is required to be set by both
             # dcbz and stores, so use the exact same function.
             # it would be better to add an extra argument to
             # set_wr_addr to indicate "dcbz mode".
-            self.___use_wr_addr_instead_set_dcbz_addr(m, pi.addr.data)
+            #self.___use_wr_addr_instead_set_dcbz_addr(m, pi.addr.data)
 
         # if now in "ST" mode: likewise do the same but with "ST"
         # to memory, acknowledge address, and send out LD data