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[soc.git] / src / soc / experiment / score6600.py

diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py
index ee4a4cd51820bcc7a726c9a697d6d24187602d5f..babce2439233f84c262c08795b873a6167197ec9 100644 (file)
--- a/src/soc/experiment/score6600.py
+++ b/src/soc/experiment/score6600.py
@@ -15,6 +15,7 @@ from soc.scoreboard.memfu import MemFunctionUnits
 
 from compalu import ComputationUnitNoDelay
 from compldst import LDSTCompUnit
+from testmem import TestMemory
 
 from alu_hier import ALU, BranchALU
 from nmutil.latch import SRLatch
@@ -25,19 +26,6 @@ from copy import deepcopy
 from math import log
 
 
-class TestMemory(Elaboratable):
-    def __init__(self, regwid, addrw):
-        self.ddepth = 1 # regwid //8
-        depth = (1<<addrw) // self.ddepth
-        self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
-
-    def elaborate(self, platform):
-        m = Module()
-        m.submodules.rdport = self.rdport = self.mem.read_port()
-        m.submodules.wrport = self.wrport = self.mem.write_port()
-        return m
-
-
 class MemSim:
     def __init__(self, regwid, addrw):
         self.regwid = regwid
@@ -110,12 +98,12 @@ class CompUnitsBase(Elaboratable):
         self.busy_o = Signal(n_units, reset_less=True)
         self.rd_rel_o = Signal(n_units, reset_less=True)
         self.req_rel_o = Signal(n_units, reset_less=True)
+        self.done_o = Signal(n_units, reset_less=True)
         if ldstmode:
             self.ld_o = Signal(n_units, reset_less=True) # op is LD
             self.st_o = Signal(n_units, reset_less=True) # op is ST
             self.adr_rel_o = Signal(n_units, reset_less=True)
             self.sto_rel_o = Signal(n_units, reset_less=True)
-            self.req_rel_o = Signal(n_units, reset_less=True)
             self.load_mem_o = Signal(n_units, reset_less=True)
             self.stwd_mem_o = Signal(n_units, reset_less=True)
             self.addr_o = Signal(rwid, reset_less=True)
@@ -138,11 +126,13 @@ class CompUnitsBase(Elaboratable):
         issue_l = []
         busy_l = []
         req_rel_l = []
+        done_l = []
         rd_rel_l = []
         shadow_l = []
         godie_l = []
         for alu in self.units:
             req_rel_l.append(alu.req_rel_o)
+            done_l.append(alu.done_o)
             rd_rel_l.append(alu.rd_rel_o)
             shadow_l.append(alu.shadown_i)
             godie_l.append(alu.go_die_i)
@@ -152,6 +142,7 @@ class CompUnitsBase(Elaboratable):
             busy_l.append(alu.busy_o)
         comb += self.rd_rel_o.eq(Cat(*rd_rel_l))
         comb += self.req_rel_o.eq(Cat(*req_rel_l))
+        comb += self.done_o.eq(Cat(*done_l))
         comb += self.busy_o.eq(Cat(*busy_l))
         comb += Cat(*godie_l).eq(self.go_die_i)
         comb += Cat(*shadow_l).eq(self.shadown_i)
@@ -464,7 +455,7 @@ class Scoreboard(Elaboratable):
 
         # LDST Comp Units
         n_ldsts = 2
-        cul = CompUnitLDSTs(self.rwid, 4, self.lsissue.n_insns, None)
+        cul = CompUnitLDSTs(self.rwid, 4, self.lsissue.n_insns, self.mem)
 
         # Comp Units
         m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cul, cub])
@@ -561,9 +552,9 @@ class Scoreboard(Elaboratable):
         # issue_i.  multi-issue gets a bit more complex but not a lot.
         prior_ldsts = Signal(cul.n_units, reset_less=True)
         sync += prior_ldsts.eq(memfus.g_int_ld_pend_o | memfus.g_int_st_pend_o)
-        with m.If(self.ls_oper_i[2]): # LD bit of operand
+        with m.If(self.ls_oper_i[3]): # LD bit of operand
             comb += memfus.ld_i.eq(cul.issue_i | prior_ldsts)
-        with m.If(self.ls_oper_i[3]): # ST bit of operand
+        with m.If(self.ls_oper_i[2]): # ST bit of operand
             comb += memfus.st_i.eq(cul.issue_i | prior_ldsts)
 
         # TODO: adr_rel_o needs to go into L1 Cache.  for now,
@@ -579,7 +570,7 @@ class Scoreboard(Elaboratable):
         go_st_i = Signal(cul.n_units, reset_less=True)
         go_ld_i = Signal(cul.n_units, reset_less=True)
         comb += go_ld_i.eq(memfus.loadable_o & memfus.addr_nomatch_o &\
-                                  cul.req_rel_o & cul.ld_o)
+                                  cul.adr_rel_o & cul.ld_o)
         comb += go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\
                                   cul.sto_rel_o & cul.st_o)
         comb += memfus.go_ld_i.eq(go_ld_i)
@@ -622,7 +613,7 @@ class Scoreboard(Elaboratable):
         # Connect Picker
         #---------
         comb += intpick1.rd_rel_i[0:n_intfus].eq(cu.rd_rel_o[0:n_intfus])
-        comb += intpick1.req_rel_i[0:n_intfus].eq(cu.req_rel_o[0:n_intfus])
+        comb += intpick1.req_rel_i[0:n_intfus].eq(cu.done_o[0:n_intfus])
         int_rd_o = intfus.readable_o
         int_wr_o = intfus.writable_o
         comb += intpick1.readable_i[0:n_intfus].eq(int_rd_o[0:n_intfus])
@@ -1137,9 +1128,9 @@ def scoreboard_sim(dut, alusim):
 
         # set random values in the registers
         for i in range(1, dut.n_regs):
-            val = randint(0, (1<<alusim.rwidth)-1)
+            #val = randint(0, (1<<alusim.rwidth)-1)
             #val = 31+i*3
-            #val = i
+            val = i
             yield dut.intregs.regs[i].reg.eq(val)
             alusim.setval(i, val)
 
@@ -1148,8 +1139,8 @@ def scoreboard_sim(dut, alusim):
         if False:
             instrs = create_random_ops(dut, 15, True, 4)
 
-        if False: # LD/ST test (with immediate)
-            instrs.append( (1, 2, 0, 0x10, 1, 1, (0, 0)) )
+        if True: # LD/ST test (with immediate)
+            instrs.append( (1, 2, 0, 0x20, 1, 1, (0, 0)) ) # LD
             #instrs.append( (1, 2, 0, 0x10, 1, 1, (0, 0)) )
 
         if True:
@@ -1280,7 +1271,7 @@ def scoreboard_sim(dut, alusim):
 def test_scoreboard():
     dut = IssueToScoreboard(2, 1, 1, 16, 8, 8)
     alusim = RegSim(16, 8)
-    memsim = MemSim(16, 16)
+    memsim = MemSim(16, 8)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_scoreboard6600.il", "w") as f:
         f.write(vl)