good grief, finally tracked down a piece of missing code in the MMU

[soc.git] / src / soc / experiment / test / pagetables.py

diff --git a/src/soc/experiment/test/pagetables.py b/src/soc/experiment/test/pagetables.py
index 885c0744402e018b0f88653eb312855da0d932c5..d1dcd579027c3db030f4aaa3d1bbb64ba4f5a393 100644 (file)
--- a/src/soc/experiment/test/pagetables.py
+++ b/src/soc/experiment/test/pagetables.py
@@ -51,7 +51,8 @@ test2 = {
 
 # microwatt mmu.bin first part of test 2. PRTBL must be set to 0x12000, PID to 1
 microwatt_test2 = {
-             0x10000: 0x0930010000000080, # leaf node
+             0x13920: 0x86810000000000c0, # leaf node
+             0x10000: 0x0930010000000080, # directory node
              0x12010: 0x0a00010000000000, # page table
              0x8108: 0x0000000badc0ffee,  # memory to be looked up
             }