Handle newer nMigen adding a "bench" hierarchy root in VCD files

[soc.git] / src / soc / experiment / test / test_compalu_multi.py

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index 2f858b6cfa2f628821177bf8bceeb4b57bcb8e38..2f2c51d1c18888187c4d540e54fb5604d9b8e236 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -58,6 +58,7 @@ class OperandProducer:
         # transaction parameters, passed via signals
         self.delay = Signal(8)
         self.data = Signal.like(self.port)
+        self.data_valid = False
         # add ourselves to the simulation process list
         sim.add_sync_process(self._process)
 
@@ -72,6 +73,7 @@ class OperandProducer:
                 yield
                 yield Settle()
             # read the transaction parameters
+            assert self.data_valid, "an unexpected operand was consumed"
             delay = (yield self.delay)
             data = (yield self.data)
             # wait for `delay` cycles
@@ -82,6 +84,7 @@ class OperandProducer:
             yield self.port.eq(data)
             yield self.count.eq(self.count + 1)
             yield
+            self.data_valid = False
             yield self.go_i.eq(0)
             yield self.port.eq(0)
 
@@ -99,6 +102,7 @@ class OperandProducer:
         """
         yield self.data.eq(data)
         yield self.delay.eq(delay)
+        self.data_valid = True
 
 
 class ResultConsumer:
@@ -127,6 +131,7 @@ class ResultConsumer:
         # transaction parameters, passed via signals
         self.delay = Signal(8)
         self.expected = Signal.like(self.port)
+        self.expecting = False
         # add ourselves to the simulation process list
         sim.add_sync_process(self._process)
 
@@ -141,6 +146,7 @@ class ResultConsumer:
                 yield
                 yield Settle()
             # read the transaction parameters
+            assert self.expecting, "an unexpected result was produced"
             delay = (yield self.delay)
             expected = (yield self.expected)
             # wait for `delay` cycles
@@ -171,6 +177,7 @@ class ResultConsumer:
         """
         yield self.expected.eq(expected)
         yield self.delay.eq(delay)
+        self.expecting = True
 
 
 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
@@ -457,13 +464,6 @@ def scoreboard_sim(op):
                         wrmask=[0, 1],
                         src_delays=[2, 0], dest_delays=[1, 0])
 
-    # test combinatorial zero-delay operation
-    # In the test ALU, any operation other than ADD, MUL, EXTS or SHR
-    # is zero-delay, and do a subtraction.
-    # 5 - 2 = 3
-    yield from op.issue([5, 2], MicrOp.OP_CMP, [3, 0],
-                        wrmask=[0, 1],
-                        src_delays=[0, 1], dest_delays=[2, 0])
     # test all combinations of masked input ports
     # NOP does not make any request nor response
     yield from op.issue([5, 2], MicrOp.OP_NOP, [0, 0],
@@ -477,6 +477,15 @@ def scoreboard_sim(op):
     yield from op.issue([2, 0x80], MicrOp.OP_EXTSWSLI, [0xFF80, 0],
                         rdmaskn=[1, 0], wrmask=[0, 1],
                         src_delays=[1, 2], dest_delays=[1, 0])
+
+    # test combinatorial zero-delay operation
+    # In the test ALU, any operation other than ADD, MUL, EXTS or SHR
+    # is zero-delay, and do a subtraction.
+    # 5 - 2 = 3
+    yield from op.issue([5, 2], MicrOp.OP_CMP, [3, 0],
+                        wrmask=[0, 1],
+                        src_delays=[0, 1], dest_delays=[2, 0])
+
     # test with rc=1, so expect results on the CR output port
     # 5 + 2 = 7
     # 7 > 0 => CR = 0b100
@@ -520,19 +529,19 @@ def test_compunit_fsm():
             ('prev port', 'in', [
                 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
                 ({'submodule': 'p'},
-                    ['p_valid_i', 'p_ready_o'])]),
+                    ['p_i_valid', 'p_o_ready'])]),
             ('next port', 'out', [
                 'n_data_o[7:0]',
                 ({'submodule': 'n'},
-                    ['n_valid_o', 'n_ready_i'])])]),
-        ('debug', {'module': 'top'},
+                    ['n_o_valid', 'n_i_ready'])])]),
+        ('debug', {'module': 'bench'},
             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 
     write_gtkw(
         "test_compunit_fsm1.gtkw",
         "test_compunit_fsm1.vcd",
         traces, style,
-        module='top.cu'
+        module='bench.top.cu'
     )
     m = Module()
     alu = Shifter(8)
@@ -650,15 +659,15 @@ def test_compunit_regspec3():
         ('alu', {'submodule': 'alu'}, [
             ('prev port', 'in', [
                 'oper_i_None__insn_type', 'i1[15:0]',
-                'valid_i', 'ready_o']),
+                'i_valid', 'o_ready']),
             ('next port', 'out', [
-                'alu_o[15:0]', 'valid_o', 'ready_i'])])]
+                'alu_o[15:0]', 'o_valid', 'i_ready'])])]
 
     write_gtkw("test_compunit_regspec3.gtkw",
                "test_compunit_regspec3.vcd",
                traces, style,
                clk_period=1e-6,
-               module='top.cu')
+               module='bench.top.cu')
 
     inspec = [('INT', 'a', '0:15'),
               ('INT', 'b', '0:15'),
@@ -725,18 +734,18 @@ def test_compunit_regspec1():
         ('alu', {'submodule': 'alu'}, [
             ('prev port', 'in', [
                 'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',
-                'valid_i', 'ready_o']),
+                'i_valid', 'o_ready']),
             ('next port', 'out', [
-                'alu_o[15:0]', 'valid_o', 'ready_i',
+                'alu_o[15:0]', 'o_valid', 'i_ready',
                 'alu_o_ok', 'alu_cr_ok'])]),
-        ('debug', {'module': 'top'},
+        ('debug', {'module': 'bench'},
             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 
     write_gtkw("test_compunit_regspec1.gtkw",
                "test_compunit_regspec1.vcd",
                traces, style,
                clk_period=1e-6,
-               module='top.cu')
+               module='bench.top.cu')
 
     inspec = [('INT', 'a', '0:15'),
               ('INT', 'b', '0:15')]