Test first input port being masked out

[soc.git] / src / soc / experiment / test / test_compalu_multi.py

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index f27a250002b4c075b0c13fd6f95b049ae9d4ce3a..3e29593522de184591b1b115c11c50b097bc6f9c 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -458,8 +458,8 @@ def scoreboard_sim(op):
     yield from op.issue([0x80, 2], MicrOp.OP_EXTS, [0xFF80],
                         rdmaskn=[0, 1],
                         src_delays=[2, 1], dest_delays=[0])
-    # 0 (masked) + 2 = 2
-    yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
+    # sign_extend(0x80) = 0xFF80
+    yield from op.issue([2, 0x80], MicrOp.OP_EXTSWSLI, [0xFF80],
                         rdmaskn=[1, 0],
                         src_delays=[1, 2], dest_delays=[1])
     # 0 (masked) + 0 (masked) = 0