Make all ports the same size, on the test ALU

[soc.git] / src / soc / experiment / test / test_compalu_multi.py

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index f6635c320fc213b68bdacdc9669d531b0e14362e..ae4f819983e37ee1bfe048c4a5de734e202730ec 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -724,7 +724,7 @@ def test_compunit_regspec1():
     inspec = [('INT', 'a', '0:15'),
               ('INT', 'b', '0:15')]
     outspec = [('INT', 'o', '0:15'),
-               ('INT', 'cr', '0:2')]
+               ('INT', 'cr', '0:15')]
 
     regspec = (inspec, outspec)