Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

[soc.git] / src / soc / experiment / test / test_loadstore1.py

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index ebc4e584801ba21facd8cf6bddeaf8dec05bb9de..64c3b6c61e5b8958a77b387633d7144b838f0b0a 100644 (file)
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -387,6 +387,19 @@ def _test_loadstore1(dut, mem):
 
     wbget.stop = True
 
+def _test_loadstore1_ifetch_invalid(dut, mem):
+    mmu = dut.submodules.mmu
+    pi = dut.submodules.ldst.pi
+    ldst = dut.submodules.ldst # to get at DAR (NOT part of PortInterface)
+    wbget.stop = False
+
+    yield mmu.rin.prtbl.eq(0x1000000) # set process table
+    yield
+
+    # TODO
+
+    wbget.stop = True
+
 
 def test_loadstore1_ifetch():
 
@@ -439,8 +452,24 @@ def test_loadstore1_invalid():
     with sim.write_vcd('test_loadstore1_invalid.vcd'):
         sim.run()
 
+def test_loadstore1_ifetch_invalid():
+
+    m, cmpi = setup_mmu()
+
+    mem = {}
+
+    # nmigen Simulation
+    sim = Simulator(m)
+    sim.add_clock(1e-6)
+
+    sim.add_sync_process(wrap(_test_loadstore1_ifetch_invalid(m, mem)))
+    sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
+    with sim.write_vcd('test_loadstore1_invalid.vcd'):
+        sim.run()
+
 
 if __name__ == '__main__':
     test_loadstore1()
     test_loadstore1_invalid()
     test_loadstore1_ifetch()
+    test_loadstore1_ifetch_invalid()