add comment about SPRs CSV
[soc.git] / src / soc / experiment / testmem.py
index 848bab7b0cc8380c892ad4a0b696a9f8c01f1383..05101d0e3f8bbb9456dfbfc2dfd5a623dd13a923 100644 (file)
@@ -6,7 +6,7 @@ class TestMemory(Elaboratable):
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
         self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
-        self.rdport = self.mem.read_port()
+        self.rdport = self.mem.read_port() # not now transparent=False)
         self.wrport = self.mem.write_port()
 
     def elaborate(self, platform):