add extra pipeline stages to ALU FU to make timing

[soc.git] / src / soc / fu / alu / pipeline.py

diff --git a/src/soc/fu/alu/pipeline.py b/src/soc/fu/alu/pipeline.py
index 3a065b2e01b416182858b76a87a3f1e67118c103..baaf69c26cde0e599840c9258f716b55d3a93c36 100644 (file)
--- a/src/soc/fu/alu/pipeline.py
+++ b/src/soc/fu/alu/pipeline.py
@@ -4,6 +4,7 @@ from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.main_stage import ALUMainStage
 from soc.fu.alu.output_stage import ALUOutputStage
 
+
 class ALUStages(PipeModBaseChain):
     def get_chain(self):
         inp = ALUInputStage(self.pspec)
@@ -15,11 +16,47 @@ class ALUStages(PipeModBaseChain):
 class ALUBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
+        self.pspec = pspec
         self.pipe1 = ALUStages(pspec)
         self._eqs = self.connect([self.pipe1])
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.pipe = self.pipe1
+        m.submodules.pipe1 = self.pipe1
+        m.d.comb += self._eqs
+        return m
+
+class ALUStages1(PipeModBaseChain):
+    def get_chain(self):
+        inp = ALUInputStage(self.pspec)
+        return [inp]
+
+class ALUStages2(PipeModBaseChain):
+    def get_chain(self):
+        main = ALUMainStage(self.pspec)
+        return [main]
+
+
+class ALUStages3(PipeModBaseChain):
+    def get_chain(self):
+        out = ALUOutputStage(self.pspec)
+        return [out]
+
+
+class ALUBasePipe(ControlBase):
+    def __init__(self, pspec):
+        ControlBase.__init__(self)
+        self.pspec = pspec
+        self.pipe1 = ALUStages1(pspec)
+        self.pipe2 = ALUStages2(pspec)
+        self.pipe3 = ALUStages3(pspec)
+        self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
+
+    def elaborate(self, platform):
+        m = ControlBase.elaborate(self, platform)
+        m.submodules.logical_pipe1 = self.pipe1
+        m.submodules.logical_pipe2 = self.pipe2
+        m.submodules.logical_pipe3 = self.pipe3
         m.d.comb += self._eqs
         return m
+