bit of a big reorg of data structures

[soc.git] / src / soc / fu / alu / test / test_pipe_caller.py

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 5cf37307f21282435b9e886070b40f077be89290..45701eb66fe82e04dbfb0814eeb4b1a412bf8ea2 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -388,9 +388,11 @@ class TestRunner(unittest.TestCase):
         comb = m.d.comb
         instruction = Signal(32)
 
-        pdecode = create_pdecode()
+        fn_name = "ALU"
+        opkls = ALUPipeSpec.opsubsetkls
 
-        m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+        m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
+        pdecode = pdecode2.dec
 
         pspec = ALUPipeSpec(id_wid=2)
         m.submodules.alu = alu = ALUBasePipe(pspec)
@@ -415,7 +417,7 @@ class TestRunner(unittest.TestCase):
 
     def check_alu_outputs(self, alu, dec2, sim, code):
 
-        rc = yield dec2.e.do.rc.data
+        rc = yield dec2.e.do.rc.rc
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data