instantiate MMU from AllFunctionUnits

[soc.git] / src / soc / fu / compunits / compunits.py

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 65357830298c517070420cbc977022d14dc7d846..9d1c0b2022cdee73b3a7c9bf5a3609472408ab81 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -47,6 +47,7 @@ from nmigen import Elaboratable, Module
 from nmigen.cli import rtlil
 from soc.experiment.compalu_multi import MultiCompUnit
 from soc.decoder.power_enums import Function
+from soc.config.test.test_loadstore import TestMemPspec
 
 # pipeline / spec imports
 
@@ -75,6 +76,9 @@ from soc.fu.div.pipeline import DivBasePipe
 from soc.fu.div.pipe_data import DivPipeSpecFSMDivCore
 from soc.fu.div.pipe_data import DivPipeSpecDivPipeCore
 
+from soc.fu.mmu.fsm import FSMMMUStage
+from soc.fu.mmu.pipe_data import MMUPipeSpec
+
 from soc.fu.mul.pipeline import MulBasePipe
 from soc.fu.mul.pipe_data import MulPipeSpec
 
@@ -167,6 +171,13 @@ class DivFSMFunctionUnit(FunctionUnitBaseSingle):
         super().__init__(DivPipeSpecFSMDivCore, DivBasePipe, idx)
 
 
+class MMUFSMFunctionUnit(FunctionUnitBaseSingle):
+    fnunit = Function.MMU
+
+    def __init__(self, idx):
+        super().__init__(MMUPipeSpec, FSMMMUStage, idx)
+
+
 class DivPipeFunctionUnit(FunctionUnitBaseSingle):
     fnunit = Function.DIV
 
@@ -236,6 +247,7 @@ class AllFunctionUnits(Elaboratable):
                      'spr': 1,
                      'logical': 1,
                      'mul': 1,
+                     'mmu': 1,
                      'div': 1, 'shiftrot': 1}
         alus = {'alu': ALUFunctionUnit,
                 'cr': CRFunctionUnit,
@@ -243,6 +255,7 @@ class AllFunctionUnits(Elaboratable):
                 'trap': TrapFunctionUnit,
                 'spr': SPRFunctionUnit,
                 'mul': MulFunctionUnit,
+                'mmu': MMUFSMFunctionUnit,
                 'logical': LogicalFunctionUnit,
                 'shiftrot': ShiftRotFunctionUnit,
                 }
@@ -291,7 +304,12 @@ def tst_single_fus_il():
 
 
 def tst_all_fus():
-    dut = AllFunctionUnits()
+    pspec = TestMemPspec(ldst_ifacetype='testpi',
+                         imem_ifacetype='',
+                         addr_wid=48,
+                         mask_wid=8,
+                         reg_wid=64)
+    dut = AllFunctionUnits(pspec)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("all_fus.il", "w") as f:
         f.write(vl)