from openpower.decoder.power_decoder2 import PowerDecode2, get_rdflags
from openpower.decoder.power_enums import Function
from openpower.decoder.isa.all import ISA
+from openpower.decoder.isa.mem import Mem
from soc.experiment.compalu_multi import find_ok # hack
from soc.config.test.test_loadstore import TestMemPspec
# pipelines (or FSMs) the write mask is only valid at that time.
if hasattr(cu, "alu"): # ALU CompUnits
while True:
- valid_o = yield cu.alu.n.valid_o
- if valid_o:
+ o_valid = yield cu.alu.n.o_valid
+ if o_valid:
break
yield
else: # LDST CompUnit
return mem.mem
-def setup_test_memory(l0, sim):
+def setup_tst_memory(l0, test_mem):
+ # create independent Sim Mem from test values
+ sim_mem = Mem(initial_mem=test_mem)
mem = get_l0_mem(l0)
print("before, init mem", mem.depth, mem.width, mem)
for i in range(mem.depth):
- data = sim.mem.ld(i*8, 8, False)
+ data = sim_mem.ld(i*8, 8, False)
print("init ", i, hex(data))
yield mem._array[i].eq(data)
yield Settle()
- for k, v in sim.mem.mem.items():
+ for k, v in sim_mem.mem.items():
print(" %6x %016x" % (k, v))
print("before, nmigen mem dump")
for i in range(mem.depth):
self.funit = funit
self.bigendian = bigendian
- def execute(self, cu, l0, instruction, pdecode2, simdec2, test):
+ def execute(self, m, cu, l0, instruction, pdecode2, simdec2, test):
program = test.program
print("test", test.name, test.mem)
# initialise memory
if self.funit == Function.LDST:
- yield from setup_test_memory(l0, sim)
+ yield from setup_tst_memory(l0, test.mem)
pc = sim.pc.CIA.value
index = pc//4
fast_out2 = yield pdecode2.e.write_fast2.data
fast_out2_ok = yield pdecode2.e.write_fast2.ok
print("lk:", lk, fast_out2, fast_out2_ok)
- op_lk = yield cu.alu.pipe1.p.data_i.ctx.op.lk
+ op_lk = yield cu.alu.pipe1.p.i_data.ctx.op.lk
print("op_lk:", op_lk)
- print(dir(cu.alu.pipe1.n.data_o))
+ print(dir(cu.alu.pipe1.n.o_data))
fn_unit = yield pdecode2.e.do.fn_unit
fuval = self.funit.value
self.assertEqual(fn_unit & fuval, fuval)
# set operand and get inputs
yield from set_operand(cu, pdecode2, sim)
# reset read-operand mask
- rdmask = get_rdflags(pdecode2.e, cu)
+ rdmask = get_rdflags(m, pdecode2.e, cu)
#print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
#print ("decoder rdmask", rdmask)
yield cu.rdmaskn.eq(~rdmask)
# debugging issue with branch
if self.funit == Function.BRANCH:
- lr = yield cu.alu.pipe1.n.data_o.lr.data
- lr_ok = yield cu.alu.pipe1.n.data_o.lr.ok
+ lr = yield cu.alu.pipe1.n.o_data.lr.data
+ lr_ok = yield cu.alu.pipe1.n.o_data.lr.ok
print("lr:", hex(lr), lr_ok)
if self.funit == Function.LDST:
m.d.comb += cu.ad.go_i.eq(cu.ad.rel_o) # link addr direct to rel
m.d.comb += cu.st.go_i.eq(cu.st.rel_o) # link store direct to rel
else:
- m.submodules.cu = cu = self.fukls(0)
+ m.submodules.cu = cu = self.fukls(0, parent_pspec=None)
l0 = None
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
for test in self.test_data:
print(test.name)
with self.subTest(test.name):
- yield from self.execute(cu, l0, instruction,
+ yield from self.execute(m, cu, l0, instruction,
pdecode2, simdec2,
test)