import enum
from nmigen import Signal, Const
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import FUBaseData
from soc.fu.alu.pipe_data import CommonPipeSpec
from soc.fu.logical.logical_input_record import CompLogicalOpSubset
from ieee754.div_rem_sqrt_rsqrt.core import (
DivPipeCoreSetupStage, DivPipeCoreCalculateStage, DivPipeCoreFinalStage)
-class DivInputData(IntegerData):
+class DivInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('INT', 'rb', '0:63'), # RB/immediate
('XER', 'xer_so', '32'), ] # XER bit 32: SO
# output stage shared between div and mul: like ALUOutputData but no CA/32
-class DivMulOutputData(IntegerData):
+class DivMulOutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'),
('CR', 'cr_a', '0:3'),
('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
class DivPipeSpec(CommonPipeSpec):
- def __init__(self, id_wid, div_pipe_kind):
- super().__init__(id_wid=id_wid)
+ def __init__(self, id_wid, parent_pspec, div_pipe_kind):
+ super().__init__(id_wid=id_wid, parent_pspec=parent_pspec)
self.div_pipe_kind = div_pipe_kind
self.core_config = div_pipe_kind.config.core_config
- regspec = (DivInputData.regspec, DivMulOutputData.regspec)
+ regspecklses = (DivInputData, DivMulOutputData)
opsubsetkls = CompLogicalOpSubset
+class DivPipeSpecDivPipeCore(DivPipeSpec):
+ def __init__(self, id_wid, parent_pspec):
+ super().__init__(id_wid=id_wid,
+ parent_pspec=parent_pspec,
+ div_pipe_kind=DivPipeKind.DivPipeCore)
+
+
+class DivPipeSpecFSMDivCore(DivPipeSpec):
+ def __init__(self, id_wid, parent_pspec):
+ super().__init__(id_wid=id_wid,
+ parent_pspec=parent_pspec,
+ div_pipe_kind=DivPipeKind.FSMDivCore)
+
+
+class DivPipeSpecSimOnly(DivPipeSpec):
+ def __init__(self, id_wid, parent_pspec):
+ super().__init__(id_wid=id_wid,
+ parent_pspec=parent_pspec,
+ div_pipe_kind=DivPipeKind.SimOnly)
+
+
class CoreBaseData(DivInputData):
def __init__(self, pspec, core_data_class):
super().__init__(pspec)