add more debug outputs, pass dcbz to loadstore/dcache

[soc.git] / src / soc / fu / ldst / loadstore.py

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index d4db098c3e403c3904bd3144080dc160ea3894c7..47d89316406ddc78ddff4b2d71b2722b7e57f5b5 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -315,6 +315,8 @@ class LoadStore1(PortInterfaceBase):
             m.d.comb += d_out.priv_mode.eq(self.req.priv_mode)
             m.d.comb += d_out.virt_mode.eq(self.req.virt_mode)
             m.d.comb += self.align_intr.eq(self.req.align_intr)
+            m.d.comb += Display("validblip dcbz=%i addr=%x",self.req.dcbz,self.req.addr)
+            m.d.comb += d_out.dcbz.eq(self.req.dcbz)
         with m.Else():
             m.d.comb += d_out.load.eq(ldst_r.load)
             m.d.comb += d_out.byte_sel.eq(ldst_r.byte_sel)
@@ -323,6 +325,8 @@ class LoadStore1(PortInterfaceBase):
             m.d.comb += d_out.priv_mode.eq(ldst_r.priv_mode)
             m.d.comb += d_out.virt_mode.eq(ldst_r.virt_mode)
             m.d.comb += self.align_intr.eq(ldst_r.align_intr)
+            m.d.comb += Display("no_validblip dcbz=%i addr=%x",ldst_r.dcbz,ldst_r.addr)
+            m.d.comb += d_out.dcbz.eq(ldst_r.dcbz)
 
         # XXX these should be possible to remove but for some reason
         # cannot be... yet. TODO, investigate