set m_out.load from ldst_r(egister) in LoadStore1

[soc.git] / src / soc / fu / ldst / loadstore.py

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index af7cbf9238bf3e0e152fce2f74f63bc44aad37e3..57404747d1ff058cf8e579b60987519dbae7dc0b 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -321,7 +321,7 @@ class LoadStore1(PortInterfaceBase):
         # Update outputs to MMU
         m.d.comb += m_out.valid.eq(mmureq)
         m.d.comb += m_out.iside.eq(self.instr_fault)
-        m.d.comb += m_out.load.eq(self.load)
+        m.d.comb += m_out.load.eq(ldst_r.load)
         # m_out.priv <= r.priv_mode; TODO
         m.d.comb += m_out.tlbie.eq(self.tlbie)
         # m_out.mtspr <= mmu_mtspr; # TODO