dcbz symbol rename

[soc.git] / src / soc / fu / ldst / loadstore.py

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 6cfc7c01a93a9d7d61567e72c2f4cbebc10bb845..a318b6f0ac06a2ce10d1c08d6a0d671328c38546 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -138,11 +138,6 @@ class LoadStore1(PortInterfaceBase):
         m.d.comb += self.req.virt_mode.eq(msr_pr) # problem-state ==> virt
         m.d.comb += self.req.align_intr.eq(misalign)
 
-        dcbz = self.pi.is_dcbz
-        with m.If(dcbz):
-            m.d.comb += Display("set_wr_addr: is_dcbz")
-        m.d.comb += self.req.dcbz.eq(dcbz)
-
         # option to disable the cache entirely for write
         if self.disable_cache:
             m.d.comb += self.req.nc.eq(1)