convert from public static functions/properties for regspecs

[soc.git] / src / soc / fu / ldst / pipe_data.py

diff --git a/src/soc/fu/ldst/pipe_data.py b/src/soc/fu/ldst/pipe_data.py
index 089e601435d83937b9db6ba335ab3e08cbc872bf..caf8bf5a15fca0dc01692225738ca70b00ae60bf 100644 (file)
--- a/src/soc/fu/ldst/pipe_data.py
+++ b/src/soc/fu/ldst/pipe_data.py
@@ -1,68 +1,36 @@
-from nmigen import Signal, Const
-from soc.fu.alu.alu_input_record import CompLDSTOpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.decoder.power_decoder2 import Data
-
-
-class LDSTInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('INT', 'rc', '0:63'),
-               ('XER', 'xer_so', '32')]
+from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
+from openpower.exceptions import LDSTException
+
+# XXX NOTE: neither of these are actually used at present other than regspecs
+# TODO: make use of them in LDSTCompUnit (somehow)
+
+class LDSTInputData(FUBaseData):
+    regspec = [('INT', 'ra', '0:63'), # RA
+               ('INT', 'rb', '0:63'), # RB/immediate
+               ('INT', 'rc', '0:63'), # RC
+               # XXX TODO, later ('XER', 'xer_so', '32') # XER bit 32: SO
                ]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB/immediate
-        self.rc = Signal(64, reset_less=True) # RC
-        self.xer_so = Signal(reset_less=True) # XER bit 32: SO
+        super().__init__(pspec, False)
         # convenience
         self.rs = self.rc
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
-        yield self.rc
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb), self.rc.eq(i.rc),
-                      self.xer_so.eq(i.xer_so)]
 
-
-class LDSTOutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
-               ('INT', 'o1', '0:63'),
+class LDSTOutputData(FUBaseData):
+    # these need to tie up with LDSTCompUnit.get_out index numbers
+    # LDSTCompUnit is unusual in that it's non-standard to RegSpecAPI
+    regspec = [('INT', 'o', '0:63'),   # RT
+               ('INT', 'o1', '0:63'),  # RA (effective address, update mode)
                ('CR', 'cr_a', '0:3'),
-               ('XER', 'xer_so', '32')]
+               # TODO, later ('XER', 'xer_so', '32')
+                ]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Data(64, name="stage_o")
-        self.o1 = Data(64, name="o1")
-        self.cr_a = Data(4, name="cr_a")
-        self.xer_so = Data(1, name="xer_so")
+        super().__init__(pspec, True, LDSTException)
         # convenience
         self.cr0, self.ea = self.cr_a, self.o1
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.o1
-        yield self.xer_ca
-        yield self.cr_a
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.o1.eq(i.o1),
-                      self.cr_a.eq(i.cr_a),
-                      self.xer_so.eq(i.xer_so)]
-
 
 class LDSTPipeSpec(CommonPipeSpec):
-    regspec = (LDSTInputData.regspec, LDSTOutputData.regspec)
+    regspecklses = (LDSTInputData, LDSTOutputData)
     opsubsetkls = CompLDSTOpSubset