rename invert_a to invert_in because logical inverts RB

[soc.git] / src / soc / fu / logical / logical_input_record.py

diff --git a/src/soc/fu/logical/logical_input_record.py b/src/soc/fu/logical/logical_input_record.py
index 3e6780382c1f17a8790ec1ec49c46d36aa13a528..ad30488adcf7b55a0dcef959ac9355a005455316 100644 (file)
--- a/src/soc/fu/logical/logical_input_record.py
+++ b/src/soc/fu/logical/logical_input_record.py
@@ -16,7 +16,7 @@ class CompLogicalOpSubset(CompOpSubsetBase):
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
-                  ('invert_a', 1),
+                  ('invert_in', 1),
                   ('zero_a', 1),
                   ('input_carry', CryIn),
                   ('invert_out', 1),