fix up Logical pipeline to produce HDL with XLEN=32

[soc.git] / src / soc / fu / logical / pipe_data.py

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 7113773337798eb62bc082ddb0acde56deba91da..359a2a595689ed66b5b15f2789e92b7a90b90998 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -1,60 +1,51 @@
-from nmigen import Signal, Const
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData
-from soc.decoder.power_decoder2 import Data
+from soc.fu.pipe_data import FUBaseData
 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 
 
-class LogicalInputData(IntegerData):
-    regspec = [('INT', 'a', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('XER', 'xer_ca', '34,45')]
+# input (and output) for logical initial stage (common input)
+class LogicalInputData(FUBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.a = Signal(64, reset_less=True) # RA
-        self.b = Signal(64, reset_less=True) # RB/immediate
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
-
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.a
-        yield self.b
-        yield self.xer_ca
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.a.eq(i.a), self.b.eq(i.b),
-                      self.xer_ca.eq(i.xer_ca) ]
-
-
-class LogicalOutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
-               ('CR', 'cr0', '0:3'),
-               ('XER', 'xer_ca', '34,45'),
-               ('XER', 'xer_so', '32')]
+        super().__init__(pspec, False)
+        # convenience
+        self.a, self.b = self.ra, self.rb
+
+    @property
+    def regspec(self):
+        return [('INT', 'ra', self.intrange),  # RA
+               ('INT', 'rb', self.intrange),  # RB/immediate
+               ('XER', 'xer_so', '32'),    # bit0: so
+               ]
+
+# input to logical final stage (common output)
+class LogicalOutputData(FUBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Data(64, name="stage_o")  # RT
-        self.cr0 = Data(4, name="cr0")
-        self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
-        self.xer_so = Data(1, name="xer_so")
-
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.xer_ca
-        yield self.cr0
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.cr0.eq(i.cr0),
-                      self.xer_so.eq(i.xer_so)]
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+
+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
+               ('CR', 'cr_a', '0:3'),
+               ('XER', 'xer_so', '32'),    # bit0: so
+               ]
+
+
+# output from logical final stage (common output) - note that XER.so
+# is *not* included (the only reason it's in the input is because of CR0)
+class LogicalOutputDataFinal(FUBaseData):
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
+               ('CR', 'cr_a', '0:3'),
+               ]
 
 
 class LogicalPipeSpec(CommonPipeSpec):
-    regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
+    regspecklses = (LogicalInputData, LogicalOutputDataFinal)
     opsubsetkls = CompLogicalOpSubset