-from nmigen import Signal, Const
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import IntegerData
+from soc.fu.pipe_data import FUBaseData
+from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
+from soc.fu.logical.logical_input_record import CompLogicalOpSubset
-class LogicalInputData(IntegerData):
+# input (and output) for logical initial stage (common input)
+class LogicalInputData(FUBaseData):
+ regspec = [('INT', 'ra', '0:63'), # RA
+ ('INT', 'rb', '0:63'), # RB/immediate
+ ('XER', 'xer_so', '32'), # bit0: so
+ ]
def __init__(self, pspec):
- super().__init__(pspec)
- self.a = Signal(64, reset_less=True) # RA
- self.b = Signal(64, reset_less=True) # RB/immediate
- self.so = Signal(reset_less=True)
- self.carry_in = Signal(reset_less=True)
-
- def __iter__(self):
- yield from super().__iter__()
- yield self.a
- yield self.b
- yield self.carry_in
- yield self.so
-
- def eq(self, i):
- lst = super().eq(i)
- return lst + [self.a.eq(i.a), self.b.eq(i.b),
- self.carry_in.eq(i.carry_in),
- self.so.eq(i.so)]
+ super().__init__(pspec, False)
+ # convenience
+ self.a, self.b = self.ra, self.rb
+
+
+# input to logical final stage (common output)
+class LogicalOutputData(FUBaseData):
+ regspec = [('INT', 'o', '0:63'), # RT
+ ('CR', 'cr_a', '0:3'),
+ ('XER', 'xer_so', '32'), # bit0: so
+ ]
+ def __init__(self, pspec):
+ super().__init__(pspec, True)
+ # convenience
+ self.cr0 = self.cr_a
+
+
+# output from logical final stage (common output) - note that XER.so
+# is *not* included (the only reason it's in the input is because of CR0)
+class LogicalOutputDataFinal(FUBaseData):
+ regspec = [('INT', 'o', '0:63'), # RT
+ ('CR', 'cr_a', '0:3'),
+ ]
+ def __init__(self, pspec):
+ super().__init__(pspec, True)
+ # convenience
+ self.cr0 = self.cr_a
+
+
+class LogicalPipeSpec(CommonPipeSpec):
+ regspecklses = (LogicalInputData, LogicalOutputDataFinal)
+ opsubsetkls = CompLogicalOpSubset