convert from public static functions/properties for regspecs

[soc.git] / src / soc / fu / logical / pipe_data.py

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 42a31ca10a89a473932cf5de16ab54234a76ffd0..40a18bc214a6ac6a6a652238ae9c24570a856c07 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -1,10 +1,10 @@
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import FUBaseData
 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 
 
 # input (and output) for logical initial stage (common input)
-class LogicalInputData(IntegerData):
+class LogicalInputData(FUBaseData):
     regspec = [('INT', 'ra', '0:63'), # RA
                ('INT', 'rb', '0:63'), # RB/immediate
                ('XER', 'xer_so', '32'),    # bit0: so
@@ -16,7 +16,7 @@ class LogicalInputData(IntegerData):
 
 
 # input to logical final stage (common output)
-class LogicalOutputData(IntegerData):
+class LogicalOutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ('CR', 'cr_a', '0:3'),
                ('XER', 'xer_so', '32'),    # bit0: so
@@ -29,7 +29,7 @@ class LogicalOutputData(IntegerData):
 
 # output from logical final stage (common output) - note that XER.so
 # is *not* included (the only reason it's in the input is because of CR0)
-class LogicalOutputDataFinal(IntegerData):
+class LogicalOutputDataFinal(FUBaseData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ('CR', 'cr_a', '0:3'),
                ]
@@ -40,5 +40,5 @@ class LogicalOutputDataFinal(IntegerData):
 
 
 class LogicalPipeSpec(CommonPipeSpec):
-    regspec = (LogicalInputData.regspec, LogicalOutputDataFinal.regspec)
+    regspecklses = (LogicalInputData, LogicalOutputDataFinal)
     opsubsetkls = CompLogicalOpSubset