convert from public static functions/properties for regspecs

[soc.git] / src / soc / fu / logical / pipe_data.py

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 6512324d67e144954d5465aad268a2a0a7200e49..40a18bc214a6ac6a6a652238ae9c24570a856c07 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -1,64 +1,44 @@
-from nmigen import Signal, Const, Cat
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData
-from soc.decoder.power_decoder2 import Data
+from soc.fu.pipe_data import FUBaseData
 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 
 
-class LogicalInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('INT', 'rb', '0:63'),
+# input (and output) for logical initial stage (common input)
+class LogicalInputData(FUBaseData):
+    regspec = [('INT', 'ra', '0:63'), # RA
+               ('INT', 'rb', '0:63'), # RB/immediate
+               ('XER', 'xer_so', '32'),    # bit0: so
                ]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB/immediate
+        super().__init__(pspec, False)
         # convenience
         self.a, self.b = self.ra, self.rb
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
 
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb),
-                       ]
-
-
-class LogicalOutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
+# input to logical final stage (common output)
+class LogicalOutputData(FUBaseData):
+    regspec = [('INT', 'o', '0:63'),        # RT
                ('CR', 'cr_a', '0:3'),
-               ('XER', 'xer_ca', '34,45'),
+               ('XER', 'xer_so', '32'),    # bit0: so
                ]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Data(64, name="stage_o")  # RT
-        self.cr_a = Data(4, name="cr_a")
-        self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
+        super().__init__(pspec, True)
         # convenience
         self.cr0 = self.cr_a
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.xer_ca
-        yield self.cr_a
 
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.cr_a.eq(i.cr_a),
-                      ]
+# output from logical final stage (common output) - note that XER.so
+# is *not* included (the only reason it's in the input is because of CR0)
+class LogicalOutputDataFinal(FUBaseData):
+    regspec = [('INT', 'o', '0:63'),        # RT
+               ('CR', 'cr_a', '0:3'),
+               ]
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
 
 
 class LogicalPipeSpec(CommonPipeSpec):
-    regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
+    regspecklses = (LogicalInputData, LogicalOutputDataFinal)
     opsubsetkls = CompLogicalOpSubset
-    def rdflags(self, e): # in order of regspec
-        reg1_ok = e.read_reg1.ok # RA
-        reg2_ok = e.read_reg2.ok # RB
-        return Cat(reg1_ok, reg2_ok) # RA RB