convert from public static functions/properties for regspecs

[soc.git] / src / soc / fu / mmu / pipe_data.py

diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py
index 2c2a45ca7b3e7814e76cd1d77699cad56529d3f2..7272a2256a3117fa2f554fe617e1eec75d7e1d84 100644 (file)
--- a/src/soc/fu/mmu/pipe_data.py
+++ b/src/soc/fu/mmu/pipe_data.py
@@ -10,16 +10,16 @@ Links:
 * https://libre-soc.org/3d_gpu/architecture/regfile/
 """
 
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import FUBaseData
 from soc.fu.mmu.mmu_input_record import CompMMUOpSubset
 from soc.fu.alu.pipe_data import CommonPipeSpec
+from openpower.exceptions import LDSTException
 
 
-class MMUInputData(IntegerData):
+class MMUInputData(FUBaseData):
     regspec = [('INT', 'ra', '0:63'),        # RA
                ('INT', 'rb', '0:63'),        # RB
                ('SPR', 'spr1', '0:63'),      # MMU (slow)
-               ('FAST', 'fast1', '0:63'),    # MMU (fast: LR, CTR etc)
                ]   
     def __init__(self, pspec):
         super().__init__(pspec, False)
@@ -28,15 +28,14 @@ class MMUInputData(IntegerData):
         self.b = self.rb
 
 
-class MMUOutputData(IntegerData):
+class MMUOutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ('SPR', 'spr1', '0:63'),     # MMU (slow)
-               ('FAST', 'fast1', '0:63'),   # MMU (fast: LR, CTR etc)
                ]
     def __init__(self, pspec):
-        super().__init__(pspec, True)
+        super().__init__(pspec, True, LDSTException)
 
 
 class MMUPipeSpec(CommonPipeSpec):
-    regspec = (MMUInputData.regspec, MMUOutputData.regspec)
+    regspecklses = (MMUInputData, MMUOutputData)
     opsubsetkls = CompMMUOpSubset