convert from public static functions/properties for regspecs

[soc.git] / src / soc / fu / mmu / pipe_data.py

diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py
index 4116a7813a4c1843cea7dae98f44f6bd62410e02..7272a2256a3117fa2f554fe617e1eec75d7e1d84 100644 (file)
--- a/src/soc/fu/mmu/pipe_data.py
+++ b/src/soc/fu/mmu/pipe_data.py
@@ -3,38 +3,39 @@
 Covers MFMMU and MTMMU for MMU MMUs (dsisr, dar), and DCBZ and TLBIE.
 
 Interestingly none of the MMU instructions use RA, they all use RB.
-go with it...
+except dcbz which uses (RA|0)
 
 Links:
 * https://bugs.libre-soc.org/show_bug.cgi?id=491
 * https://libre-soc.org/3d_gpu/architecture/regfile/
 """
 
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import FUBaseData
 from soc.fu.mmu.mmu_input_record import CompMMUOpSubset
 from soc.fu.alu.pipe_data import CommonPipeSpec
+from openpower.exceptions import LDSTException
 
 
-class MMUInputData(IntegerData):
-    regspec = [('INT', 'rb', '0:63'),        # RB
+class MMUInputData(FUBaseData):
+    regspec = [('INT', 'ra', '0:63'),        # RA
+               ('INT', 'rb', '0:63'),        # RB
                ('SPR', 'spr1', '0:63'),      # MMU (slow)
-               ('FAST', 'fast1', '0:63'),    # MMU (fast: LR, CTR etc)
                ]   
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
+        self.a = self.ra
         self.b = self.rb
 
 
-class MMUOutputData(IntegerData):
+class MMUOutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ('SPR', 'spr1', '0:63'),     # MMU (slow)
-               ('FAST', 'fast1', '0:63'),   # MMU (fast: LR, CTR etc)
                ]
     def __init__(self, pspec):
-        super().__init__(pspec, True)
+        super().__init__(pspec, True, LDSTException)
 
 
 class MMUPipeSpec(CommonPipeSpec):
-    regspec = (MMUInputData.regspec, MMUOutputData.regspec)
+    regspecklses = (MMUInputData, MMUOutputData)
     opsubsetkls = CompMMUOpSubset