from soc.fu.mul.mul_input_record import CompMULOpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.div.pipe_data import DIVInputData, DivMulOutputData
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
+from soc.fu.div.pipe_data import DivInputData, DivMulOutputData
from nmigen import Signal
-class MulIntermediateData(DIVInputData):
+class MulIntermediateData(DivInputData):
def __init__(self, pspec):
super().__init__(pspec)
self.data.append(self.neg_res32)
-class MulOutputData(IntegerData):
- regspec = [('INT', 'o', '0:128'),
- ('XER', 'xer_so', '32')] # XER bit 32: SO
+class MulOutputData(FUBaseData):
def __init__(self, pspec):
super().__init__(pspec, False) # still input style
self.data.append(self.neg_res)
self.data.append(self.neg_res32)
+ @property
+ def regspec(self):
+ return [('INT', 'o', "0:%d" % (self.pspec.XLEN)),
+ ('XER', 'xer_so', '32')] # XER bit 32: SO
+
class MulPipeSpec(CommonPipeSpec):
- regspec = (DIVInputData.regspec, DivMulOutputData.regspec)
+ regspecklses = (DivInputData, DivMulOutputData)
opsubsetkls = CompMULOpSubset