-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.alu.pipe_data import ALUOutputData, ALUInputData
+from soc.fu.mul.mul_input_record import CompMULOpSubset
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
+from soc.fu.div.pipe_data import DivInputData, DivMulOutputData
+from nmigen import Signal
-class MulIntermediateData(ALUInputData):
+class MulIntermediateData(DivInputData):
def __init__(self, pspec):
super().__init__(pspec)
- neg_result = Signal(reset_less=True)
- self.data.append(neg_result)
+ self.neg_res = Signal(reset_less=True)
+ self.neg_res32 = Signal(reset_less=True)
+ self.data.append(self.neg_res)
+ self.data.append(self.neg_res32)
-class MulOutputData(IntegerData):
- regspec = [('INT', 'o', '0:128'),
- ('XER', 'xer_so', '32'), # XER bit 32: SO
- ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
+class MulOutputData(FUBaseData):
def __init__(self, pspec):
- super().__init__(pspec, False)
+ super().__init__(pspec, False) # still input style
- neg_result = Signal(reset_less=True)
- self.data.append(neg_result)
+ self.neg_res = Signal(reset_less=True)
+ self.neg_res32 = Signal(reset_less=True)
+ self.data.append(self.neg_res)
+ self.data.append(self.neg_res32)
+
+ @property
+ def regspec(self):
+ return [('INT', 'o', "0:%d" % (self.pspec.XLEN)),
+ ('XER', 'xer_so', '32')] # XER bit 32: SO
class MulPipeSpec(CommonPipeSpec):
- regspec = (ALUInputData.regspec, ALUOutputData.regspec)
- opsubsetkls = CompALUOpSubset
+ regspecklses = (DivInputData, DivMulOutputData)
+ opsubsetkls = CompMULOpSubset