start on converting MUL and DIV pipelines to XLEN

[soc.git] / src / soc / fu / mul / pipe_data.py

diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py
index 495d503b4ff1bffffb02e251b19cb64a2c92dd80..ded4c5089a56dd22319a2343324830a9a99bd8f6 100644 (file)
--- a/src/soc/fu/mul/pipe_data.py
+++ b/src/soc/fu/mul/pipe_data.py
@@ -1,10 +1,34 @@
-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.alu.pipe_data import ALUOutputData
-from soc.fu.shift_rot.pipe_data import ShoftRotInputData
+from soc.fu.mul.mul_input_record import CompMULOpSubset
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
+from soc.fu.div.pipe_data import DivInputData, DivMulOutputData
+from nmigen import Signal
 
 
-# TODO: replace CompALUOpSubset with CompShiftRotOpSubset
-class ShiftRotPipeSpec(CommonPipeSpec):
-    regspec = (ShiftRotInputData.regspec, ALUOutputData.regspec)
-    opsubsetkls = CompALUOpSubset
+class MulIntermediateData(DivInputData):
+    def __init__(self, pspec):
+        super().__init__(pspec)
+
+        self.neg_res = Signal(reset_less=True)
+        self.neg_res32 = Signal(reset_less=True)
+        self.data.append(self.neg_res)
+        self.data.append(self.neg_res32)
+
+
+class MulOutputData(FUBaseData):
+    def __init__(self, pspec):
+        super().__init__(pspec, False) # still input style
+
+        self.neg_res = Signal(reset_less=True)
+        self.neg_res32 = Signal(reset_less=True)
+        self.data.append(self.neg_res)
+        self.data.append(self.neg_res32)
+
+    @property
+    def regspec(self):
+        return [('INT', 'o', "0:%d" % (self.pspec.XLEN)),
+               ('XER', 'xer_so', '32')] # XER bit 32: SO
+
+
+class MulPipeSpec(CommonPipeSpec):
+    regspecklses = (DivInputData, DivMulOutputData)
+    opsubsetkls = CompMULOpSubset