start on converting MUL and DIV pipelines to XLEN

[soc.git] / src / soc / fu / mul / pipe_data.py

diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py
index eef6cd837f1e6dd370a7de7867788fab00fcf75b..ded4c5089a56dd22319a2343324830a9a99bd8f6 100644 (file)
--- a/src/soc/fu/mul/pipe_data.py
+++ b/src/soc/fu/mul/pipe_data.py
@@ -1,10 +1,10 @@
 from soc.fu.mul.mul_input_record import CompMULOpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.div.pipe_data import DIVInputData, DivMulOutputData
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
+from soc.fu.div.pipe_data import DivInputData, DivMulOutputData
 from nmigen import Signal
 
 
-class MulIntermediateData(DIVInputData):
+class MulIntermediateData(DivInputData):
     def __init__(self, pspec):
         super().__init__(pspec)
 
@@ -14,10 +14,7 @@ class MulIntermediateData(DIVInputData):
         self.data.append(self.neg_res32)
 
 
-class MulOutputData(IntegerData):
-    regspec = [('INT', 'o', '0:128'),
-               ('XER', 'xer_so', '32'), # XER bit 32: SO
-               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
+class MulOutputData(FUBaseData):
     def __init__(self, pspec):
         super().__init__(pspec, False) # still input style
 
@@ -26,7 +23,12 @@ class MulOutputData(IntegerData):
         self.data.append(self.neg_res)
         self.data.append(self.neg_res32)
 
+    @property
+    def regspec(self):
+        return [('INT', 'o', "0:%d" % (self.pspec.XLEN)),
+               ('XER', 'xer_so', '32')] # XER bit 32: SO
+
 
 class MulPipeSpec(CommonPipeSpec):
-    regspec = (DIVInputData.regspec, DivMulOutputData.regspec)
+    regspecklses = (DivInputData, DivMulOutputData)
     opsubsetkls = CompMULOpSubset