-# This stage is intended to do most of the work of executing multiply
+# This stage is intended to prepare the multiplication operands
+
from nmigen import (Module, Signal, Mux)
from nmutil.pipemodbase import PipeModBase
-from soc.fu.alu.pipe_data import ALUInputData
+from soc.fu.div.pipe_data import DivInputData
from soc.fu.mul.pipe_data import MulIntermediateData
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
from nmutil.util import eq32
class MulMainStage1(PipeModBase):
super().__init__(pspec, "mul1")
def ispec(self):
- return ALUInputData(self.pspec) # defines pipeline stage input format
+ return DivInputData(self.pspec) # defines pipeline stage input format
def ospec(self):
return MulIntermediateData(self.pspec) # pipeline stage output format
def elaborate(self, platform):
+ XLEN = self.pspec.XLEN
m = Module()
comb = m.d.comb
comb += is_32bit.eq(op.is_32bit)
# work out if a/b are negative (check 32-bit / signed)
- comb += sign_a.eq(Mux(op.is_32bit, a[31], a[63]) & op.is_signed)
- comb += sign_b.eq(Mux(op.is_32bit, b[31], b[63]) & op.is_signed)
+ comb += sign_a.eq(Mux(op.is_32bit, a[31], a[XLEN-1]) & op.is_signed)
+ comb += sign_b.eq(Mux(op.is_32bit, b[31], b[XLEN-1]) & op.is_signed)
comb += sign32_a.eq(a[31] & op.is_signed)
comb += sign32_b.eq(b[31] & op.is_signed)
# negation of a 64-bit value produces the same lower 32-bit
# result as negation of just the lower 32-bits, so we don't
# need to do anything special before negating
- abs_a = Signal(64, reset_less=True)
- abs_b = Signal(64, reset_less=True)
+ abs_a = Signal(XLEN, reset_less=True)
+ abs_b = Signal(XLEN, reset_less=True)
comb += abs_a.eq(Mux(sign_a, -a, a))
comb += abs_b.eq(Mux(sign_b, -b, b))
###### XER and context, both pass-through #####
- comb += self.o.xer_ca.eq(self.i.xer_ca)
comb += self.o.xer_so.eq(self.i.xer_so)
comb += self.o.ctx.eq(self.i.ctx)