add EXTSWSLI "pass" to formal shift_rot proof

[soc.git] / src / soc / fu / shift_rot / formal / proof_main_stage.py

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index 685b221f5641e20628b00eeafa9f7cb10f076133..6346950da5599f0ecd8d6a36d993f52896c864cb 100644 (file)
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -103,6 +103,8 @@ class Driver(Elaboratable):
                 pass
             with m.Case(MicrOp.OP_RLCL):
                 pass
+            with m.Case(MicrOp.OP_EXTSWSLI):
+                pass
             with m.Default():
                 comb += o_ok.eq(0)