remove grev, leaving tests for later use with grevlut

[soc.git] / src / soc / fu / shift_rot / main_stage.py

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index b8ec704199a800c6df652524612581e07d885bb2..2735927839b73d1d8f13f9713f9c9f1fe3b00192 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -8,6 +8,7 @@
 # output stage
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
+from soc.fu.pipe_data import get_pspec_draft_bitmanip
 from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData,
                                         ShiftRotInputData)
 from nmutil.lut import BitwiseLut
@@ -21,6 +22,7 @@ from openpower.decoder.power_fieldsn import SignalBitRange
 class ShiftRotMainStage(PipeModBase):
     def __init__(self, pspec):
         super().__init__(pspec, "main")
+        self.draft_bitmanip = get_pspec_draft_bitmanip(pspec)
         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
         self.fields.create_specs()
 
@@ -31,16 +33,19 @@ class ShiftRotMainStage(PipeModBase):
         return ShiftRotOutputData(self.pspec)
 
     def elaborate(self, platform):
+        XLEN = self.pspec.XLEN
         m = Module()
         comb = m.d.comb
         op = self.i.ctx.op
         o = self.o.o
 
-        bitwise_lut = BitwiseLut(input_count=3, width=64)
-        m.submodules.bitwise_lut = bitwise_lut
-        comb += bitwise_lut.inputs[0].eq(self.i.rb)
-        comb += bitwise_lut.inputs[1].eq(self.i.ra)
-        comb += bitwise_lut.inputs[2].eq(self.i.rc)
+        bitwise_lut = None
+        if self.draft_bitmanip:
+            bitwise_lut = BitwiseLut(input_count=3, width=XLEN)
+            m.submodules.bitwise_lut = bitwise_lut
+            comb += bitwise_lut.inputs[0].eq(self.i.rb)
+            comb += bitwise_lut.inputs[1].eq(self.i.ra)
+            comb += bitwise_lut.inputs[2].eq(self.i.rc)
 
         # NOTE: the sh field immediate is read in by PowerDecode2
         # (actually DecodeRB), whereupon by way of rb "immediate" mode
@@ -57,7 +62,7 @@ class ShiftRotMainStage(PipeModBase):
         comb += mb_extra.eq(md_fields['mb'][0:-1][0])
 
         # set up microwatt rotator module
-        m.submodules.rotator = rotator = Rotator()
+        m.submodules.rotator = rotator = Rotator(XLEN)
         comb += [
             rotator.me.eq(me),
             rotator.mb.eq(mb),
@@ -71,12 +76,17 @@ class ShiftRotMainStage(PipeModBase):
 
         comb += o.ok.eq(1)  # defaults to enabled
 
+        # instruction rotate type
+        mode = Signal(4, reset_less=True)
+        comb += Cat(rotator.right_shift,
+                    rotator.clear_left,
+                    rotator.clear_right,
+                    rotator.sign_ext_rs).eq(mode)
+
         # outputs from the microwatt rotator module
         comb += [o.data.eq(rotator.result_o),
                  self.o.xer_ca.data.eq(Repl(rotator.carry_out_o, 2))]
 
-        # instruction rotate type
-        mode = Signal(4, reset_less=True)
         with m.Switch(op.insn_type):
             with m.Case(MicrOp.OP_SHL):
                 comb += mode.eq(0b0000)  # L-shift
@@ -90,20 +100,16 @@ class ShiftRotMainStage(PipeModBase):
                 comb += mode.eq(0b0100)  # clear R
             with m.Case(MicrOp.OP_EXTSWSLI):
                 comb += mode.eq(0b1000)  # L-ext
-            with m.Case(MicrOp.OP_TERNLOG):
-                # TODO: this only works for ternaryi, change to get lut value
-                # from register when we implement other variants
-                comb += bitwise_lut.lut.eq(self.fields.FormTLI.TLI[:])
-                comb += o.data.eq(bitwise_lut.output)
-                comb += self.o.xer_ca.data.eq(0)
+            if self.draft_bitmanip:
+                with m.Case(MicrOp.OP_TERNLOG):
+                    # TODO: this only works for ternlogi, change to get lut
+                    # value from register when we implement other variants
+                    comb += bitwise_lut.lut.eq(self.fields.FormTLI.TLI[:])
+                    comb += o.data.eq(bitwise_lut.output)
+                    comb += self.o.xer_ca.data.eq(0)
             with m.Default():
                 comb += o.ok.eq(0)  # otherwise disable
 
-        comb += Cat(rotator.right_shift,
-                    rotator.clear_left,
-                    rotator.clear_right,
-                    rotator.sign_ext_rs).eq(mode)
-
         ###### sticky overflow and context, both pass-through #####
 
         comb += self.o.xer_so.data.eq(self.i.xer_so)