convert from public static functions/properties for regspecs

[soc.git] / src / soc / fu / shift_rot / pipe_data.py

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 5c34a6921e942f60eaf189f448df3ad6972c32dd..276320dbcaead42bdf79a08098a9207202139a79 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -1,43 +1,46 @@
-from nmigen import Signal, Const, Cat
-from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.shift_rot.sr_input_record import CompSROpSubset
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.logical.pipe_data import LogicalOutputData
-from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
+from soc.fu.alu.pipe_data import ALUOutputData
 
 
-class ShiftRotInputData(IntegerData):
-    regspec = [('INT', 'a', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('INT', 'rs', '0:63'),
-               ('XER', 'xer_ca', '34,45')]
+class ShiftRotInputData(FUBaseData):
+    regspec = [('INT', 'ra', '0:63'),      # RA
+               ('INT', 'rb', '0:63'),      # RB
+               ('INT', 'rc', '0:63'),      # RS
+               ('XER', 'xer_so', '32'), # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.a = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB/immediate
-        self.rs = Signal(64, reset_less=True) # RS
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
-
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.a
-        yield self.rb
-        yield self.rs
-        yield self.xer_ca
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.rs.eq(i.rs), self.a.eq(i.a),
-                      self.rb.eq(i.rb),
-                      self.xer_ca.eq(i.xer_ca) ]
+        super().__init__(pspec, False)
+        # convenience
+        self.a, self.b, self.rs = self.ra, self.rb, self.rc
+
+
+# input to shiftrot final stage (common output)
+class ShiftRotOutputData(FUBaseData):
+    regspec = [('INT', 'o', '0:63'),        # RT
+               ('CR', 'cr_a', '0:3'),
+               ('XER', 'xer_so', '32'),    # bit0: so
+               ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
+               ]
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+
+
+# output from shiftrot final stage (common output) - note that XER.so
+# is *not* included (the only reason it's in the input is because of CR0)
+class ShiftRotOutputDataFinal(FUBaseData):
+    regspec = [('INT', 'o', '0:63'),        # RT
+               ('CR', 'cr_a', '0:3'),
+               ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
+               ]
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
 
 
 class ShiftRotPipeSpec(CommonPipeSpec):
-    regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
+    regspecklses = (ShiftRotInputData, ShiftRotOutputDataFinal)
     opsubsetkls = CompSROpSubset
-    def rdflags(self, e): # in order of regspec input
-        reg1_ok = e.read_reg1.ok # RA
-        reg2_ok = e.read_reg2.ok # RB
-        reg3_ok = e.read_reg3.ok # RS
-        return Cat(reg1_ok, reg2_ok, reg3_ok, 1) # RA RB RC CA