convert from public static functions/properties for regspecs

[soc.git] / src / soc / fu / shift_rot / pipe_data.py

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index adafe1af08e77152c25f4b46d5fc07540234ca6e..276320dbcaead42bdf79a08098a9207202139a79 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -1,9 +1,9 @@
 from soc.fu.shift_rot.sr_input_record import CompSROpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
 from soc.fu.alu.pipe_data import ALUOutputData
 
 
-class ShiftRotInputData(IntegerData):
+class ShiftRotInputData(FUBaseData):
     regspec = [('INT', 'ra', '0:63'),      # RA
                ('INT', 'rb', '0:63'),      # RB
                ('INT', 'rc', '0:63'),      # RS
@@ -16,7 +16,7 @@ class ShiftRotInputData(IntegerData):
 
 
 # input to shiftrot final stage (common output)
-class ShiftRotOutputData(IntegerData):
+class ShiftRotOutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ('CR', 'cr_a', '0:3'),
                ('XER', 'xer_so', '32'),    # bit0: so
@@ -30,7 +30,7 @@ class ShiftRotOutputData(IntegerData):
 
 # output from shiftrot final stage (common output) - note that XER.so
 # is *not* included (the only reason it's in the input is because of CR0)
-class ShiftRotOutputDataFinal(IntegerData):
+class ShiftRotOutputDataFinal(FUBaseData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ('CR', 'cr_a', '0:3'),
                ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
@@ -42,5 +42,5 @@ class ShiftRotOutputDataFinal(IntegerData):
 
 
 class ShiftRotPipeSpec(CommonPipeSpec):
-    regspec = (ShiftRotInputData.regspec, ShiftRotOutputDataFinal.regspec)
+    regspecklses = (ShiftRotInputData, ShiftRotOutputDataFinal)
     opsubsetkls = CompSROpSubset