convert shift_rot pipeline to XLEN=32/64

[soc.git] / src / soc / fu / shift_rot / pipe_data.py

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 42b70db6f3c6487821a27eafd152b014c6328cdf..d783d017ed3851ea2dbb55b2f56b2e20d2ef66eb 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -1,30 +1,55 @@
-from nmigen import Signal, Const
-from nmutil.dynamicpipe import SimpleHandshakeRedir
-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import IntegerData
+from soc.fu.shift_rot.sr_input_record import CompSROpSubset
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
+from soc.fu.alu.pipe_data import ALUOutputData
 
 
-class ShiftRotInputData(IntegerData):
+class ShiftRotInputData(FUBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rs = Signal(64, reset_less=True) # RS
-        self.rb = Signal(64, reset_less=True) # RB/immediate
-        self.so = Signal(reset_less=True)
-        self.carry_in = Signal(reset_less=True)
-
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rs
-        yield self.rb
-        yield self.carry_in
-        yield self.so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.rs.eq(i.rs), self.ra.eq(i.ra),
-                      self.rb.eq(i.rb),
-                      self.carry_in.eq(i.carry_in),
-                      self.so.eq(i.so)]
+        super().__init__(pspec, False)
+        # convenience
+        self.a, self.b, self.rs = self.ra, self.rb, self.rc
+
+    @property
+    def regspec(self):
+        return [('INT', 'ra', self.intrange),  # RA
+               ('INT', 'rb', self.intrange),  # RB/immediate
+               ('INT', 'rc', self.intrange),  # RB/immediate
+               ('XER', 'xer_so', '32'), # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
+
+
+# input to shiftrot final stage (common output)
+class ShiftRotOutputData(FUBaseData):
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+
+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
+               ('CR', 'cr_a', '0:3'),
+               ('XER', 'xer_so', '32'),    # bit0: so
+               ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
+               ]
+
+
+# output from shiftrot final stage (common output) - note that XER.so
+# is *not* included (the only reason it's in the input is because of CR0)
+class ShiftRotOutputDataFinal(FUBaseData):
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+
+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
+               ('CR', 'cr_a', '0:3'),
+               ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
+               ]
+
+
+class ShiftRotPipeSpec(CommonPipeSpec):
+    regspecklses = (ShiftRotInputData, ShiftRotOutputDataFinal)
+    opsubsetkls = CompSROpSubset