convert shift_rot pipeline to XLEN=32/64

[soc.git] / src / soc / fu / shift_rot / pipe_data.py

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 46d383a0300421a18b75f5c6d748f601d1c586af..d783d017ed3851ea2dbb55b2f56b2e20d2ef66eb 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -1,45 +1,55 @@
-from nmigen import Signal, Const, Cat
-from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.shift_rot.sr_input_record import CompSROpSubset
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.logical.pipe_data import LogicalOutputData
-from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
+from soc.fu.alu.pipe_data import ALUOutputData
 
 
-class ShiftRotInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('INT', 'rc', '0:63'),
-               ('XER', 'xer_ca', '34,45')]
+class ShiftRotInputData(FUBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB
-        self.rc = Signal(64, reset_less=True) # RS
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
+        super().__init__(pspec, False)
         # convenience
-        self.a, self.rs = self.ra, self.rc
+        self.a, self.b, self.rs = self.ra, self.rb, self.rc
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
-        yield self.rc
-        yield self.xer_ca
+    @property
+    def regspec(self):
+        return [('INT', 'ra', self.intrange),  # RA
+               ('INT', 'rb', self.intrange),  # RB/immediate
+               ('INT', 'rc', self.intrange),  # RB/immediate
+               ('XER', 'xer_so', '32'), # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
 
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.rc.eq(i.rc), self.ra.eq(i.ra),
-                      self.rb.eq(i.rb),
-                      self.xer_ca.eq(i.xer_ca) ]
+
+# input to shiftrot final stage (common output)
+class ShiftRotOutputData(FUBaseData):
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+
+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
+               ('CR', 'cr_a', '0:3'),
+               ('XER', 'xer_so', '32'),    # bit0: so
+               ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
+               ]
+
+
+# output from shiftrot final stage (common output) - note that XER.so
+# is *not* included (the only reason it's in the input is because of CR0)
+class ShiftRotOutputDataFinal(FUBaseData):
+    def __init__(self, pspec):
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+
+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
+               ('CR', 'cr_a', '0:3'),
+               ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
+               ]
 
 
 class ShiftRotPipeSpec(CommonPipeSpec):
-    regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
+    regspecklses = (ShiftRotInputData, ShiftRotOutputDataFinal)
     opsubsetkls = CompSROpSubset
-    def rdflags(self, e): # in order of regspec input
-        reg1_ok = e.read_reg1.ok # RA
-        reg2_ok = e.read_reg2.ok # RB
-        reg3_ok = e.read_reg3.ok # RS
-        return Cat(reg1_ok, reg2_ok, reg3_ok, 1) # RA RB RC CA