add simulator test against qemu for extswsli

[soc.git] / src / soc / fu / shift_rot / test / test_pipe_caller.py

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index c1b20b1a9de8e1407ba7a9f9b0d10b98abc18dc5..9c5701ee562897779676d1d9e67a72e589c243da 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -146,7 +146,7 @@ class ShiftRotTestCase(FHDLTestCase):
             sh = random.randint(0, 63)
             lst = [f"extswsli 3, 1, {sh}"]
             initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<64)-1)
+            initial_regs[1] = random.randint(0, (1<<15)-1)
             self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rlc(self):