enable extswsli tests, fix spec-patching

[soc.git] / src / soc / fu / shift_rot / test / test_pipe_caller.py

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 5a56f0176e477c89da7113254f3daac6819a3152..f19ba4d3e618aace90f3ed62f299380a6c598644 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -148,7 +148,7 @@ class ShiftRotTestCase(FHDLTestCase):
         initial_regs[1] = 0x5678
         self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def tst_extswsli(self):
+    def test_extswsli(self):
         for i in range(40):
             sh = random.randint(0, 63)
             lst = [f"extswsli 3, 1, {sh}"]