split out CompOpSubsetBase (meaning to do for a while)

[soc.git] / src / soc / fu / spr / spr_input_record.py

diff --git a/src/soc/fu/spr/spr_input_record.py b/src/soc/fu/spr/spr_input_record.py
index 84599a98163c3049c2e29dda7fc0d1d1fbb2a8af..72402d3eed17d4df81674b60729be766be2ddcf0 100644 (file)
--- a/src/soc/fu/spr/spr_input_record.py
+++ b/src/soc/fu/spr/spr_input_record.py
@@ -1,9 +1,8 @@
-from nmigen.hdl.rec import Record, Layout
 
 from soc.decoder.power_enums import (MicrOp, Function)
+from soc.fu.base_input_record import CompOpSubsetBase
 
-
-class CompSPROpSubset(Record):
+class CompSPROpSubset(CompOpSubsetBase):
     """CompSPROpSubset
 
     a copy of the relevant subset information from Decode2Execute1Type
@@ -16,27 +15,4 @@ class CompSPROpSubset(Record):
                   ('insn', 32),
                   ('is_32bit', 1),
                   )
-
-        Record.__init__(self, Layout(layout), name=name)
-
-        # grrr.  Record does not have kwargs
-        self.insn_type.reset_less = True
-        self.insn.reset_less = True
-        self.fn_unit.reset_less = True
-        self.is_32bit.reset_less = True
-
-    def eq_from_execute1(self, other):
-        """ use this to copy in from Decode2Execute1Type
-        """
-        res = []
-        for fname, sig in self.fields.items():
-            eqfrom = other.do.fields[fname]
-            res.append(sig.eq(eqfrom))
-        return res
-
-    def ports(self):
-        return [self.insn_type,
-                self.insn,
-                self.fn_unit,
-                self.is_32bit,
-        ]
+        super().__init__(layout, name=name)