LDSTException now passing bits of SRR1 around to the Trap Pipeline

[soc.git] / src / soc / fu / trap / main_stage.py

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 9eb85887d14db0d472426ed6a1c78fbb6a42b492..f0da82b9d24200f64dc3927cc524bc89a9e2e80d 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -67,7 +67,9 @@ class TrapMainStage(PipeModBase):
         msr_i = op.msr
         svstate_i = op.svstate
 
-        srr1_i = self.i.srr1
+        exc = LDSTException("trapexc")
+        comb += exc.eq(op.ldst_exc)
+        srr1_i = exc.srr1 # new SRR1 bits come from exception
         nia_o = self.o.nia
         svsrr0_o, srr0_o, srr1_o = self.o.svsrr0, self.o.srr0, self.o.srr1