convert from public static functions/properties for regspecs

[soc.git] / src / soc / fu / trap / pipe_data.py

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index a43c214c65031f0c8ba99526a75bb95dee462a35..b9c829bccc1811a1e7e334aba22fc3b09e7a907d 100644 (file)
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -1,35 +1,40 @@
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
 from soc.fu.trap.trap_input_record import CompTrapOpSubset
 
 
-class TrapInputData(IntegerData):
+class TrapInputData(FUBaseData):
     regspec = [('INT', 'ra', '0:63'),  # RA
                ('INT', 'rb', '0:63'),  # RB/immediate
                ('FAST', 'fast1', '0:63'), # SRR0
                ('FAST', 'fast2', '0:63'), # SRR1
-               ('FAST', 'cia', '0:63'),  # Program counter (current)
-               ('FAST', 'msr', '0:63')]  # MSR
+               ('FAST', 'fast3', '0:63'), # SVSRR0
+                # note here that MSR CIA and SVSTATE are *not* read as regs:
+                # they are passed in as incoming "State", via the
+                # CompTrapOpSubset
+               ] 
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
-        self.srr0, self.srr1 = self.fast1, self.fast2
+        self.srr0, self.srr1, self.svsrr0 = self.fast1, self.fast2, self.fast3
         self.a, self.b = self.ra, self.rb
 
 
-class TrapOutputData(IntegerData):
+class TrapOutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),     # RA
                ('FAST', 'fast1', '0:63'), # SRR0 SPR
                ('FAST', 'fast2', '0:63'), # SRR1 SPR
-               ('FAST', 'nia', '0:63'),  # NIA (Next PC)
-               ('FAST', 'msr', '0:63')]  # MSR
+               ('FAST', 'fast3', '0:63'), # SRR2 SPR
+               # ... however we *do* need to *write* MSR, NIA, SVSTATE (RFID)
+               ('STATE', 'nia', '0:63'),  # NIA (Next PC)
+               ('STATE', 'msr', '0:63'),  # MSR
+               ('STATE', 'svstate', '0:63')]  # SVSTATE
     def __init__(self, pspec):
         super().__init__(pspec, True)
         # convenience
-        self.srr0, self.srr1 = self.fast1, self.fast2
+        self.srr0, self.srr1, self.svsrr0 = self.fast1, self.fast2, self.fast3
 
 
 
-# TODO: replace CompALUOpSubset with CompTrapOpSubset
 class TrapPipeSpec(CommonPipeSpec):
-    regspec = (TrapInputData.regspec, TrapOutputData.regspec)
+    regspecklses = (TrapInputData, TrapOutputData)
     opsubsetkls = CompTrapOpSubset