+"""trap pipeline tests
+
+issues:
+* https://bugs.libre-soc.org/show_bug.cgi?id=629
+"""
+
from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmutil.formaltest import FHDLTestCase
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
-
-
-from soc.fu.test.common import TestCase
-#from soc.fu.cr.pipeline import CRBasePipe
-#from soc.fu.cr.pipe_data import CRPipeSpec
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import XER_bits, Function
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.isa.all import ISA
+from openpower.endian import bigendian
+from openpower.consts import MSR
+
+from openpower.test.common import TestAccumulatorBase, ALUHelpers
+from soc.fu.trap.pipeline import TrapBasePipe
+from soc.fu.trap.pipe_data import TrapPipeSpec
import random
+from openpower.test.trap.trap_cases import TrapTestCase
+
+
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to TrapFunctionUnit input regspec
+ """
+ res = {}
+
+ yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
+ yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
+ yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR0
+ yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2) # SPR1
+ yield from ALUHelpers.get_sim_fast_spr3(res, sim, dec2) # SVSRR0
+ ALUHelpers.get_sim_cia(res, sim, dec2) # PC
+ ALUHelpers.get_sim_msr(res, sim, dec2) # MSR
+
+ print("alu get_cu_inputs", res)
+
+ return res
+
+
+def set_alu_inputs(alu, dec2, sim):
+ # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
+ # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
+ # and place it into i_data.b
+
+ inp = yield from get_cu_inputs(dec2, sim)
+ yield from ALUHelpers.set_int_ra(alu, dec2, inp)
+ yield from ALUHelpers.set_int_rb(alu, dec2, inp)
+ yield from ALUHelpers.set_fast_spr1(alu, dec2, inp) # SPR0
+ yield from ALUHelpers.set_fast_spr2(alu, dec2, inp) # SPR1
+ yield from ALUHelpers.set_fast_spr3(alu, dec2, inp) # SVSRR0
+
+ # yield from ALUHelpers.set_cia(alu, dec2, inp)
+ # yield from ALUHelpers.set_msr(alu, dec2, inp)
+ return inp
+
+class TrapIlangCase(TestAccumulatorBase):
-# This test bench is a bit different than is usual. Initially when I
-# was writing it, I had all of the tests call a function to create a
-# device under test and simulator, initialize the dut, run the
-# simulation for ~2 cycles, and assert that the dut output what it
-# should have. However, this was really slow, since it needed to
-# create and tear down the dut and simulator for every test case.
-
-# Now, instead of doing that, every test case in ALUTestCase puts some
-# data into the test_data list below, describing the instructions to
-# be tested and the initial state. Once all the tests have been run,
-# test_data gets passed to TestRunner which then sets up the DUT and
-# simulator once, runs all the data through it, and asserts that the
-# results match the pseudocode sim at every cycle.
-
-# By doing this, I've reduced the time it takes to run the test suite
-# massively. Before, it took around 1 minute on my computer, now it
-# takes around 3 seconds
-
-
-class TrapTestCase(FHDLTestCase):
- test_data = []
- def __init__(self, name):
- super().__init__(name)
- self.test_name = name
-
-
-# def get_cu_inputs(dec2, sim):
-# """naming (res) must conform to CRFunctionUnit input regspec
-# """
-# res = {}
-# full_reg = yield dec2.e.read_cr_whole
-#
-# # full CR
-# print(sim.cr.get_range().value)
-# if full_reg:
-# res['full_cr'] = sim.cr.get_range().value
-# else:
-# # CR A
-# cr1_en = yield dec2.e.read_cr1.ok
-# if cr1_en:
-# cr1_sel = yield dec2.e.read_cr1.data
-# res['cr_a'] = sim.crl[cr1_sel].get_range().value
-# cr2_en = yield dec2.e.read_cr2.ok
-# # CR B
-# if cr2_en:
-# cr2_sel = yield dec2.e.read_cr2.data
-# res['cr_b'] = sim.crl[cr2_sel].get_range().value
-# cr3_en = yield dec2.e.read_cr3.ok
-# # CR C
-# if cr3_en:
-# cr3_sel = yield dec2.e.read_cr3.data
-# res['cr_c'] = sim.crl[cr3_sel].get_range().value
-#
-# # RA/RC
-# reg1_ok = yield dec2.e.read_reg1.ok
-# if reg1_ok:
-# data1 = yield dec2.e.read_reg1.data
-# res['ra'] = sim.gpr(data1).value
-#
-# # RB (or immediate)
-# reg2_ok = yield dec2.e.read_reg2.ok
-# if reg2_ok:
-# data2 = yield dec2.e.read_reg2.data
-# res['rb'] = sim.gpr(data2).value
-#
-# print ("get inputs", res)
-# return res
-
-
-class TestRunner(FHDLTestCase):
+ def case_ilang(self):
+ pspec = TrapPipeSpec(id_wid=2, parent_pspec=None)
+ alu = TrapBasePipe(pspec)
+ vl = rtlil.convert(alu, ports=alu.ports())
+ with open("trap_pipeline.il", "w") as f:
+ f.write(vl)
+
+
+class TestRunner(unittest.TestCase):
def __init__(self, test_data):
super().__init__("run_all")
self.test_data = test_data
-# def set_inputs(self, alu, dec2, simulator):
-# inp = yield from get_cu_inputs(dec2, simulator)
-# if 'full_cr' in inp:
-# yield alu.p.data_i.full_cr.eq(inp['full_cr'])
-# else:
-# yield alu.p.data_i.full_cr.eq(0)
-# if 'cr_a' in inp:
-# yield alu.p.data_i.cr_a.eq(inp['cr_a'])
-# if 'cr_b' in inp:
-# yield alu.p.data_i.cr_b.eq(inp['cr_b'])
-# if 'cr_c' in inp:
-# yield alu.p.data_i.cr_c.eq(inp['cr_c'])
-# if 'ra' in inp:
-# yield alu.p.data_i.ra.eq(inp['ra'])
-# else:
-# yield alu.p.data_i.ra.eq(0)
-# if 'rb' in inp:
-# yield alu.p.data_i.rb.eq(inp['rb'])
-# else:
-# yield alu.p.data_i.rb.eq(0)
-#
-# def assert_outputs(self, alu, dec2, simulator, code):
-# whole_reg = yield dec2.e.write_cr_whole
-# cr_en = yield dec2.e.write_cr.ok
-# if whole_reg:
-# full_cr = yield alu.n.data_o.full_cr.data
-# expected_cr = simulator.cr.get_range().value
-# self.assertEqual(expected_cr, full_cr, code)
-# elif cr_en:
-# cr_sel = yield dec2.e.write_cr.data
-# expected_cr = simulator.crl[cr_sel].get_range().value
-# real_cr = yield alu.n.data_o.cr.data
-# self.assertEqual(expected_cr, real_cr, code)
-# alu_out = yield alu.n.data_o.o.data
-# out_reg_valid = yield dec2.e.write_reg.ok
-# if out_reg_valid:
-# write_reg_idx = yield dec2.e.write_reg.data
-# expected = simulator.gpr(write_reg_idx).value
-# print(f"expected {expected:x}, actual: {alu_out:x}")
-# self.assertEqual(expected, alu_out, code)
+
+ def execute(self, alu, instruction, pdecode2, test):
+ program = test.program
+ sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem, test.msr,
+ bigendian=bigendian)
+ gen = program.generate_instructions()
+ instructions = list(zip(gen, program.assembly.splitlines()))
+
+ msr = sim.msr.value
+ pc = sim.pc.CIA.value
+ print("starting msr, pc %08x, %08x" % (msr, pc))
+ index = pc//4
+ while index < len(instructions):
+ ins, code = instructions[index]
+
+ print("pc %08x msr %08x instr: %08x" % (pc, msr, ins))
+ print(code)
+ if 'XER' in sim.spr:
+ so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+ ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
+ ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
+ print("before: so/ov/32", so, ov, ov32)
+
+ # ask the decoder to decode this binary data (endian'd)
+ yield pdecode2.dec.bigendian.eq(bigendian) # l/big?
+ yield pdecode2.state.msr.eq(msr) # set MSR in pdecode2
+ yield pdecode2.state.pc.eq(pc) # set CIA in pdecode2
+ yield instruction.eq(ins) # raw binary instr.
+ yield Settle()
+ fn_unit = yield pdecode2.e.do.fn_unit
+ asmcode = yield pdecode2.e.asmcode
+ dec_asmcode = yield pdecode2.dec.op.asmcode
+ print("asmcode", asmcode, dec_asmcode)
+ self.assertEqual(fn_unit, Function.TRAP.value)
+ alu_o = yield from set_alu_inputs(alu, pdecode2, sim)
+
+ # set valid for one cycle, propagate through pipeline...
+ yield alu.p.i_valid.eq(1)
+ yield
+ yield alu.p.i_valid.eq(0)
+
+ opname = code.split(' ')[0]
+ yield from sim.call(opname)
+ pc = sim.pc.CIA.value
+ index = pc//4
+ print("pc after %08x" % (pc))
+ msr = sim.msr.value
+ print("msr after %08x" % (msr))
+
+ vld = yield alu.n.o_valid
+ while not vld:
+ yield
+ vld = yield alu.n.o_valid
+ yield
+
+ yield from self.check_alu_outputs(alu, pdecode2, sim, code)
+ yield Settle()
def run_all(self):
m = Module()
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
-# pspec = CRPipeSpec(id_wid=2)
-# m.submodules.alu = alu = CRBasePipe(pspec)
-#
-# comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
-# comb += alu.n.ready_i.eq(1)
+ pspec = TrapPipeSpec(id_wid=2, parent_pspec=None)
+ m.submodules.alu = alu = TrapBasePipe(pspec)
+
+ comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
+ comb += alu.n.i_ready.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
sim.add_clock(1e-6)
+
def process():
for test in self.test_data:
print(test.name)
program = test.program
- self.subTest(test.name)
- sim = ISA(pdecode2, test.regs, test.sprs, test.cr)
- gen = program.generate_instructions()
- instructions = list(zip(gen, program.assembly.splitlines()))
-
- index = sim.pc.CIA.value//4
- while index < len(instructions):
- ins, code = instructions[index]
-
- print("0x{:X}".format(ins & 0xffffffff))
- print(code)
-
- # ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(0) # little / big?
- yield instruction.eq(ins) # raw binary instr.
- yield Settle()
- yield from self.set_inputs(alu, pdecode2, sim)
- yield alu.p.valid_i.eq(1)
- fn_unit = yield pdecode2.e.fn_unit
- self.assertEqual(fn_unit, Function.CR.value, code)
- yield
- opname = code.split(' ')[0]
- yield from sim.call(opname)
- index = sim.pc.CIA.value//4
-
- vld = yield alu.n.valid_o
- while not vld:
- yield
- vld = yield alu.n.valid_o
- yield
- yield from self.assert_outputs(alu, pdecode2, sim, code)
+ with self.subTest(test.name):
+ yield from self.execute(alu, instruction, pdecode2, test)
sim.add_sync_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
+ with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
+ traces=[]):
sim.run()
+ def check_alu_outputs(self, alu, dec2, sim, code):
+
+ rc = yield dec2.e.do.rc.data
+ cridx_ok = yield dec2.e.write_cr.ok
+ cridx = yield dec2.e.write_cr.data
+
+ print("check extra output", repr(code), cridx_ok, cridx)
+ if rc:
+ self.assertEqual(cridx, 0, code)
+
+ sim_o = {}
+ res = {}
+
+ yield from ALUHelpers.get_int_o(res, alu, dec2)
+ yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
+ yield from ALUHelpers.get_fast_spr2(res, alu, dec2)
+ yield from ALUHelpers.get_fast_spr3(res, alu, dec2)
+ yield from ALUHelpers.get_nia(res, alu, dec2)
+ yield from ALUHelpers.get_msr(res, alu, dec2)
+
+ print("output", res)
+
+ yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_fast_spr2(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_fast_spr3(sim_o, sim, dec2)
+ ALUHelpers.get_sim_nia(sim_o, sim, dec2)
+ ALUHelpers.get_sim_msr(sim_o, sim, dec2)
+
+ print("sim output", sim_o)
+
+ ALUHelpers.check_int_o(self, res, sim_o, code)
+ ALUHelpers.check_fast_spr1(self, res, sim_o, code)
+ ALUHelpers.check_fast_spr2(self, res, sim_o, code)
+ ALUHelpers.check_fast_spr3(self, res, sim_o, code)
+ ALUHelpers.check_nia(self, res, sim_o, code)
+ ALUHelpers.check_msr(self, res, sim_o, code)
+
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(TrapTestCase.test_data))
+ suite.addTest(TestRunner(TrapTestCase().test_data))
+ suite.addTest(TestRunner(TrapIlangCase().test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff