adding option to include XICS external interrupts.

[soc.git] / src / soc / interrupts / xics.py

diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py
index 3cf2a1294f8b1e8f2cf69c38716c9f0d017a6f50..7709252c7c9678fb958cca8f38c0eae2c4a5e8dd 100644 (file)
--- a/src/soc/interrupts/xics.py
+++ b/src/soc/interrupts/xics.py
@@ -76,7 +76,7 @@ class XICS_ICP(Elaboratable):
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = 32
-        self.bus = Record(make_wb_layout(spec))
+        self.bus = Record(make_wb_layout(spec), name="icp_wb")
         self.ics_i = ICS2ICP("ics_i")
         self.core_irq_o = Signal()
 
@@ -226,7 +226,7 @@ class XICS_ICS(Elaboratable):
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = 32
-        self.bus = Record(make_wb_layout(spec))
+        self.bus = Record(make_wb_layout(spec), name="ics_wb")
 
         self.int_level_i = Signal(SRC_NUM)
         self.icp_o = ICS2ICP("icp_o")