add build commands to Makefile for versa ecp5

[soc.git] / src / soc / litex / florent / Makefile

diff --git a/src/soc/litex/florent/Makefile b/src/soc/litex/florent/Makefile
index 48937c303c74d59077e64bc01315e11567e72f8f..754d5d083956ec4b9df405784b30d0c6ee511972 100644 (file)
--- a/src/soc/litex/florent/Makefile
+++ b/src/soc/litex/florent/Makefile
@@ -3,7 +3,16 @@ ls180:
        cp build/ls180/gateware/ls180.v .
        cp build/ls180/gateware/mem.init .
        cp libresoc/libresoc.v .
-       yosys -p 'read_verilog ls180.v; read_verilog libresoc.v; write_ilang ls180.il'
+       yosys -p 'read_verilog libresoc.v' \
+          -p 'write_ilang libresoc_cvt.il'
        yosys -p 'read_verilog ls180.v' \
-          -p 'read_verilog libresoc.v' \
+          -p 'write_ilang ls180_cvt.il'
+       yosys -p 'read_ilang ls180_cvt.il' \
+          -p 'read_ilang libresoc_cvt.il' \
           -p 'write_ilang ls180.il'
+
+versaecp5:
+        ./versa_ecp5.py --sys-clk-freq=55e6 --build
+
+versaecp5load:
+       ./versa_ecp5.py --sys-clk-freq=55e6 --load