urk. wishbone slave devices declared incorrectly (I/O inverted)

[soc.git] / src / soc / litex / florent / libresoc / core.py

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index cf072784faf5e85c64c0723d0bc9ba7c3fd03f16..a9571eb5d249ed624ce69ff7fde14c16cbed290a 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -2,10 +2,10 @@ import os
 
 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 
-from litex.soc.interconnect import wishbone
+from litex.soc.interconnect import wishbone as wb
 from litex.soc.cores.cpu import CPU
 
-CPU_VARIANTS = ["standard", "standard32"]
+CPU_VARIANTS = ["standard", "standard32", "ls180"]
 
 
 def make_wb_bus(prefix, obj):
@@ -16,6 +16,14 @@ def make_wb_bus(prefix, obj):
         res['i_%s_%s' % (prefix, i)] = getattr(obj, i)
     return res
 
+def make_wb_slave(prefix, obj):
+    res = {}
+    for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
+        res['i_%s_%s' % (prefix, i)] = getattr(obj, i)
+    for o in ['ack', 'err', 'dat_r']:
+        res['o_%s_%s' % (prefix, o)] = getattr(obj, o)
+    return res
+
 
 class LibreSoC(CPU):
     name                 = "libre_soc"
@@ -55,16 +63,18 @@ class LibreSoC(CPU):
 
         if variant == "standard32":
             self.data_width           = 32
-            self.dbus = dbus = wishbone.Interface(data_width=32, adr_width=30)
+            self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
         else:
-            self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
+            self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
             self.data_width           = 64
-        self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
+        self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
+
+        self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
+        self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
 
-        self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=5)
-        self.xics_ics = ics = wishbone.Interface(data_width=32, adr_width=14)
+        if variant != "ls180":
+            self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
 
-        self.ics_buses = [icp, ics]
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 
@@ -104,8 +114,10 @@ class LibreSoC(CPU):
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus_", ibus))
         self.cpu_params.update(make_wb_bus("dbus_", dbus))
-        self.cpu_params.update(make_wb_bus("ics_wb_", ics))
-        self.cpu_params.update(make_wb_bus("icp_wb_", icp))
+        self.cpu_params.update(make_wb_slave("ics_wb_", ics))
+        self.cpu_params.update(make_wb_slave("icp_wb_", icp))
+        if variant != "ls180":
+            self.cpu_params.update(make_wb_slave("gpio_wb_", gpio))
 
         # add verilog sources
         self.add_sources(platform)