reduce clkcsel ls180 width (2 pins), rename pll_18 signal

[soc.git] / src / soc / litex / florent / libresoc / ls180.py

diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index 3eb9abeb8a270c248d69b5bfadf5b11852f118cd..98c117f679e290798f45d553f814d9b9f5b45b94 100644 (file)
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -49,7 +49,7 @@ def io():
         # CLK/RST: 2 pins
         ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
-        ("sys_clksel_i",   0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")),
+        ("sys_clksel_i",   0, Pins("R1 R2"), IOStandard("LVCMOS33")),
         ("sys_pll_18_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_pll_lck_o",   0, Pins("R1"), IOStandard("LVCMOS33")),