from nmigen.utils import log2_int
-__all__ = ["Cycle", "wishbone_layout", "make_wb_layout", "WishboneArbiter"]
+__all__ = ["Cycle", "make_wb_layout", "WishboneArbiter"]
class Cycle:
END = 7
-def make_wb_layout(addr_wid, mask_wid, data_wid):
+def make_wb_layout(spec, cti=True):
+ addr_wid, mask_wid, data_wid = spec.addr_wid, spec.mask_wid, spec.reg_wid
adr_lsbs = log2_int(mask_wid) # LSBs of addr covered by mask
- badwid = addr_wid-adr_lsbs # MSBs (not covered by mask)
-
- return [
+ badwid = spec.addr_wid-adr_lsbs # MSBs (not covered by mask)
+ # test if microwatt compatibility is to be enabled
+ microwatt_compat = (hasattr(spec, "microwatt_compat") and
+ (spec.microwatt_compat == True))
+ # test if fabric compatibility is to be enabled
+ fabric_compat = (hasattr(spec, "fabric_compat") and
+ (spec.fabric_compat == True))
+
+ res = [
("adr", badwid , DIR_FANOUT),
("dat_w", data_wid, DIR_FANOUT),
("dat_r", data_wid, DIR_FANIN),
("stb", 1, DIR_FANOUT),
("ack", 1, DIR_FANIN),
("we", 1, DIR_FANOUT),
- ("cti", 3, DIR_FANOUT),
- ("bte", 2, DIR_FANOUT),
("err", 1, DIR_FANIN)
]
-
-wishbone_layout = make_wb_layout(32, 4, 32)
+ # microwatt needs a stall signal (operates in pipeline mode)
+ if microwatt_compat or fabric_compat:
+ res.append(("stall", 1, DIR_FANIN))
+ if not cti:
+ return res
+ return res + [
+ ("cti", 3, DIR_FANOUT),
+ ("bte", 2, DIR_FANOUT),
+ ]
class WishboneArbiter(Elaboratable):
- def __init__(self, addr_wid=32, mask_wid=4, data_wid=32):
- self.bus = Record(make_wb_layout(addr_wid, mask_wid, data_wid))
+ def __init__(self, pspec):
+ self.bus = Record(make_wb_layout(pspec))
self._port_map = dict()
def port(self, priority):