'nia': "nia",
'msr': "msr",
'svstate': "svstate",
+ 'issue': "issue", # writing DEC/TB
+ 'state1': "state1", # SPR pipeline
# these 3 allow writing state by Issuer
'sv': "sv", # writing SVSTATE
'd_wr1': "d_wr1", # writing PC
'cia': "cia", # reading PC (issuer)
'msr': "msr", # reading MSR (issuer)
'sv': "sv", # reading SV (issuer)
+ # SPR and DEC/TB FSM
+ 'issue': "issue", # reading DEC/TB
+ 'state1': "state1", # SPR pipeline
}
return w_port_spec, r_port_spec
* Array-based unary-indexed (not binary-indexed)
* write-through capability (read on same cycle as write)
"""
- def __init__(self, svp64_en=False, regreduce_en=False):
- super().__init__(64, 32, fwd_bus_mode=False)
+ def __init__(self, svp64_en=False, regreduce_en=False, reg_wid=64):
+ super().__init__(reg_wid, 32, fwd_bus_mode=False)
self.svp64_en = svp64_en
self.regreduce_en = regreduce_en
wr_spec, rd_spec = self.get_port_specs()
class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray):
"""FastRegs
- FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC, SVSRR0
+ FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, SVSRR0
* QTY 6of 64-bit registers
* 3R2W
def get_port_specs(self):
w_port_spec = {'fast1': "dest1",
- 'issue': "issue", # writing DEC/TB
}
r_port_spec = {'fast1': "src1",
- 'issue': "issue", # reading DEC/TB
'dmi': "dmi" # needed for Debug (DMI)
}
if not self.regreduce_en:
regreduce_en = hasattr(pspec, "regreduce") and \
(pspec.regreduce == True)
+ # get Integer File register width
+ reg_wid = 64
+ if isinstance(pspec.XLEN, int):
+ reg_wid = pspec.XLEN
+
self.rf = {} # register file dict
# create regfiles here, Factory style
for (name, kls) in RegFiles.regkls:
kwargs = {'svp64_en': svp64_en, 'regreduce_en': regreduce_en}
if name == 'state':
kwargs['resets'] = state_resets
+ if name == 'int':
+ kwargs['reg_wid'] = reg_wid
rf = self.rf[name] = kls(**kwargs)
# also add these as instances, self.state, self.fast, self.cr etc.
setattr(self, name, rf)
if __name__ == '__main__':
m = Module()
from soc.config.test.test_loadstore import TestMemPspec
- pspec = TestMemPspec()
+ pspec = TestMemPspec(regreduce_en=True,
+ XLEN=32) # integer reg width = 32
rf = RegFiles(pspec, make_hazard_vecs=True)
rf.elaborate_into(m, None)
vl = rtlil.convert(m)