from nmigen import Module
from nmigen.cli import rtlil
+from nmutil.latch import SRLatch
def create_ports(rf, wr_spec, rd_spec):
(d_rd2)
"""
- def __init__(self, svp64_en=False, regreduce_en=False):
- super().__init__(64, StateRegsEnum.N_REGS)
+ def __init__(self, svp64_en=False, regreduce_en=False, resets=None):
+ super().__init__(64, StateRegsEnum.N_REGS, resets=resets)
wr_spec, rd_spec = self.get_port_specs()
create_ports(self, wr_spec, rd_spec)
def get_port_specs(self):
- w_port_spec = {'nia': "nia",
+ w_port_spec = { # these 3 allow writing state by Function Units
+ # strictly speaking this should not be allowed,
+ # the information should be passed back to Issuer
+ # to work out what to do
+ 'nia': "nia",
'msr': "msr",
'svstate': "svstate",
- 'sv': "sv", # writing SVSTATE (issuer)
- 'd_wr1': "d_wr1"} # writing PC (issuer)
- r_port_spec = {'cia': "cia", # reading PC (issuer)
+ 'issue': "issue", # writing DEC/TB
+ 'state1': "state1", # SPR pipeline
+ # these 3 allow writing state by Issuer
+ 'sv': "sv", # writing SVSTATE
+ 'd_wr1': "d_wr1", # writing PC
+ 'd_wr2': "d_wr2"} # writing MSR
+ r_port_spec = { # these are for reading state by Issuer but
+ # the FUs do not read them: they are passed in
+ # because of multi-issue / pipelining / etc.
+ # the state could be totally different and is
+ # only known *at* issue time, *by* the issuer
+ 'cia': "cia", # reading PC (issuer)
'msr': "msr", # reading MSR (issuer)
'sv': "sv", # reading SV (issuer)
+ # SPR and DEC/TB FSM
+ 'issue': "issue", # reading DEC/TB
+ 'state1': "state1", # SPR pipeline
}
return w_port_spec, r_port_spec
* Array-based unary-indexed (not binary-indexed)
* write-through capability (read on same cycle as write)
"""
- def __init__(self, svp64_en=False, regreduce_en=False):
- super().__init__(64, 32, fwd_bus_mode=not regreduce_en)
+ def __init__(self, svp64_en=False, regreduce_en=False, reg_wid=64):
+ super().__init__(reg_wid, 32, fwd_bus_mode=False)
self.svp64_en = svp64_en
self.regreduce_en = regreduce_en
wr_spec, rd_spec = self.get_port_specs()
class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray):
"""FastRegs
- FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC, SVSRR0
+ FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, SVSRR0
* QTY 6of 64-bit registers
* 3R2W
Note: r/w issue are used by issuer to increment/decrement TB/DEC.
"""
def __init__(self, svp64_en=False, regreduce_en=False):
- super().__init__(64, FastRegsEnum.N_REGS, fwd_bus_mode=not regreduce_en)
+ super().__init__(64, FastRegsEnum.N_REGS, fwd_bus_mode=False)
self.svp64_en = svp64_en
self.regreduce_en = regreduce_en
wr_spec, rd_spec = self.get_port_specs()
def get_port_specs(self):
w_port_spec = {'fast1': "dest1",
- 'issue': "issue", # writing DEC/TB
}
r_port_spec = {'fast1': "src1",
- 'issue': "issue", # reading DEC/TB
+ 'dmi': "dmi" # needed for Debug (DMI)
}
if not self.regreduce_en:
r_port_spec['fast2'] = "src2"
else:
n_sprs = len(SPRfull)
super().__init__(width=64, depth=n_sprs,
- fwd_bus_mode=not regreduce_en)
+ fwd_bus_mode=False)
self.svp64_en = svp64_en
self.regreduce_en = regreduce_en
wr_spec, rd_spec = self.get_port_specs()
('fast', FastRegs),
('state', StateRegs),
('spr', SPRRegs),]
- def __init__(self, pspec, make_hazard_vecs=False):
+ def __init__(self, pspec, make_hazard_vecs=False,
+ state_resets=None): # state file reset values
# test is SVP64 is to be enabled
svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
regreduce_en = hasattr(pspec, "regreduce") and \
(pspec.regreduce == True)
+ # get Integer File register width
+ reg_wid = 64
+ if isinstance(pspec.XLEN, int):
+ reg_wid = pspec.XLEN
+
self.rf = {} # register file dict
# create regfiles here, Factory style
for (name, kls) in RegFiles.regkls:
- rf = self.rf[name] = kls(svp64_en, regreduce_en)
+ kwargs = {'svp64_en': svp64_en, 'regreduce_en': regreduce_en}
+ if name == 'state':
+ kwargs['resets'] = state_resets
+ if name == 'int':
+ kwargs['reg_wid'] = reg_wid
+ rf = self.rf[name] = kls(**kwargs)
# also add these as instances, self.state, self.fast, self.cr etc.
setattr(self, name, rf)
def make_hazard_vec(self, rf, name):
if isinstance(rf, VirtualRegPort):
- vec = VirtualRegPort(rf.nregs, rf.nregs, wr2=True)
+ vec = SRLatch(sync=False, llen=rf.nregs, name=name)
else:
- vec = VirtualRegPort(rf.depth, rf.depth, wr2=True)
- # get read/write port specs and create bitvector ports with same names
- wr_spec, rd_spec = rf.get_port_specs()
- # ok, this is complicated/fun.
- # issue phase for checking whether to issue only needs one read port
- # however during regfile-read, the corresponding bitvector needs to
- # be *WRITTEN* to (a 1), and during regfile-write, the corresponding
- # bitvector *ALSO* needs to be wrtten (a 0). therefore we need to
- # MERGE the wr_spec and rd_spec with some appropriate name prefixes
- # to make sure they do not clash
- rd_bvspec = {'issue': 'full_rd'}
- wr_bvspec = {'set': 'full_wr', 'clr': 'full_wr2'}
- create_ports(vec, wr_bvspec, rd_bvspec)
+ vec = SRLatch(sync=False, llen=rf.depth, name=name)
return vec
def elaborate_into(self, m, platform):
if __name__ == '__main__':
m = Module()
from soc.config.test.test_loadstore import TestMemPspec
- pspec = TestMemPspec()
+ pspec = TestMemPspec(regreduce_en=True,
+ XLEN=32) # integer reg width = 32
rf = RegFiles(pspec, make_hazard_vecs=True)
rf.elaborate_into(m, None)
vl = rtlil.convert(m)
projects / soc.git / blobdiff