Enable read port for non-transparent memories

[soc.git] / src / soc / regfile / sram_wrapper.py

diff --git a/src/soc/regfile/sram_wrapper.py b/src/soc/regfile/sram_wrapper.py
index 5a455b811e6371f9db1bf69bce54eb18bab3e1c2..cba1ec21d2bc63ab7cde87aec9c4838915955409 100644 (file)
--- a/src/soc/regfile/sram_wrapper.py
+++ b/src/soc/regfile/sram_wrapper.py
@@ -340,6 +340,16 @@ class PhasedDualPortRegfile(Elaboratable):
 
         return m
 
+    def ports(self):
+        return [
+            self.wr_addr_i,
+            self.wr_data_i,
+            self.wr_we_i,
+            self.rd_addr_i,
+            self.rd_data_o,
+            self.phase
+        ]
+
 
 class PhasedDualPortRegfileTestCase(FHDLTestCase):
 
@@ -589,6 +599,10 @@ class DualPortRegfile(Elaboratable):
         lvt_mem = Memory(width=self.we_width, depth=depth)
         lvt_wr = lvt_mem.write_port(granularity=1)
         lvt_rd = lvt_mem.read_port(transparent=self.transparent)
+        if not self.transparent:
+            # for some reason, formal proofs don't recognize the default
+            # reset value for this signal
+            m.d.comb += lvt_rd.en.eq(1)
         m.submodules.lvt_wr = lvt_wr
         m.submodules.lvt_rd = lvt_rd
         # generate and wire the phases for the phased memories
@@ -660,6 +674,15 @@ class DualPortRegfile(Elaboratable):
                                    == self.dbg_wrote_phase)
         return m
 
+    def ports(self):
+        return [
+            self.wr_addr_i,
+            self.wr_data_i,
+            self.wr_we_i,
+            self.rd_addr_i,
+            self.rd_data_o
+        ]
+
 
 class DualPortRegfileTestCase(FHDLTestCase):