store cur_state.pc+4 in separate register to help reduce

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 06bfcdf3de19d13c45a7c3be60d010ed16b04e1a..4a3eb4021454fa1020423e5f5fca06c87f867701 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -436,10 +436,14 @@ class TestIssuerBase(Elaboratable):
             dbg_sync = ClockDomain(self.dbg_domain)
             m.domains += dbg_sync
 
+        # create a delay, but remember it is in the power-on-reset clock domain!
         ti_rst = Signal(reset_less=True)
         delay = Signal(range(4), reset=3)
+        stop_delay = Signal(range(16), reset=5)
         with m.If(delay != 0):
-            m.d.por += delay.eq(delay - 1)
+            m.d.por += delay.eq(delay - 1) # decrement... in POR domain!
+        with m.If(stop_delay != 0):
+            m.d.por += stop_delay.eq(stop_delay - 1) # likewise
         comb += cd_por.clk.eq(ClockSignal())
 
         # power-on reset delay
@@ -450,6 +454,9 @@ class TestIssuerBase(Elaboratable):
         else:
             with m.If(delay != 0 | dbg.core_rst_o):
                 comb += core_rst.eq(1)
+        with m.If(stop_delay != 0):
+            # run DMI core-stop as well but on an extra couple of cycles
+            comb += dbg.core_stopped_i.eq(1)
 
         # connect external reset signal to DMI Reset
         if self.dbg_domain != "sync":
@@ -462,12 +469,13 @@ class TestIssuerBase(Elaboratable):
         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 
         # temporary hack: says "go" immediately for both address gen and ST
+        # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
         l0 = core.l0
         ldst = core.fus.fus['ldst0']
         st_go_edge = rising_edge(m, ldst.st.rel_o)
         # link addr-go direct to rel
         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o)
-        m.d.comb += ldst.st.go_i.eq(st_go_edge)  # link store-go to rising rel
+        m.d.sync += ldst.st.go_i.eq(st_go_edge)  # link store-go to rising rel
 
     def do_dmi(self, m, dbg):
         """deals with DMI debug requests
@@ -807,6 +815,10 @@ class TestIssuerInternal(TestIssuerBase):
             fetch_failed = Const(0, 1)
             flush_needed = False
 
+        # create a register with pc+4 as a way to reduce combinatorial chains
+        pc4 = Signal.like(cur_state.pc)
+        sync += pc4.eq(cur_state.pc + 4)
+
         # set priv / virt mode on I-Cache, sigh
         if isinstance(self.imem, ICache):
             comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
@@ -814,6 +826,12 @@ class TestIssuerInternal(TestIssuerBase):
 
         with m.FSM(name='fetch_fsm'):
 
+            # allow fetch to not run at startup due to I-Cache reset not
+            # having time to settle.  power-on-reset holds dbg.core_stopped_i
+            with m.State("PRE_IDLE"):
+                with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o):
+                    m.next = "IDLE"
+
             # waiting (zzz)
             with m.State("IDLE"):
                 # fetch allowed if not failed and stopped but not stepping
@@ -884,7 +902,7 @@ class TestIssuerInternal(TestIssuerBase):
                                 m.next = "INSN_READY"
                             with m.Else():
                                 # fetch the rest of the instruction from memory
-                                comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
+                                comb += self.imem.a_pc_i.eq(pc4)
                                 comb += self.imem.a_i_valid.eq(1)
                                 comb += self.imem.f_i_valid.eq(1)
                                 m.next = "INSN_READ2"
@@ -911,7 +929,7 @@ class TestIssuerInternal(TestIssuerBase):
                         # blech, icache returns actual instruction
                         insn = self.imem.f_instr_o
                     else:
-                        insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
+                        insn = get_insn(self.imem.f_instr_o, pc4)
                     sync += dec_opcode_i.eq(insn)
                     m.next = "INSN_READY"
                     # TODO: probably can start looking at pdecode2.rm_dec